Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-03-08
2002-10-01
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S339000, C257S341000
Reexamination Certificate
active
06459128
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the art of field-effect transistors, and more particularly to a field-effect transistor having a high breakdown voltage, a reduced gate-to-drain capacitance, and a low conduction resistance.
2. Description of the Related Art
MOS transistors with a number of cells have heretofore been employed as power control devices.
FIG. 40
of the accompanying drawings shows a conventional MOS transistor
105
by way of example. As shown in
FIG. 40
, the conventional MOS transistor
105
has a substrate
111
of single-crystal silicon and a drain layer
112
deposited on the substrate
111
by epitaxial growth.
The substrate
111
is doped with an N-type impurity at a high concentration, and the drain layer
112
is doped with an N-type impurity at a low concentration.
A P-type impurity is diffused into the drain layer
112
from its surface, forming base regions
154
.
An N-type impurity is diffused into each of the base regions
154
from its surface, forming a ring-shaped source region
161
. A region
110
represents a surface of each of the base regions
154
that is positioned between an end of the base region
154
and an outer periphery of the source region
161
, and is referred to as a channel region. The channel region
110
, the base region
154
, and the source region
161
jointly make up a single cell
101
. The MOS transistor
105
has a number of cells
101
arranged in a regular grid pattern on the surface of the drain layer
112
.
FIG. 41
of the accompanying drawings shows the layout of the cells
101
of the MOS transistor
105
.
In each of the cells
101
, the surface of the base region
154
is exposed within the ring-shaped source region
161
. A source electrode film
144
is disposed on the surface of the source region
161
and the surface of the base region
154
in each of the cells
101
. The source region
161
and the base region
154
are connected to the source electrode film
144
.
A gate insulating film
126
comprising a silicon oxide film is disposed on the channel region
110
in each cell
101
and the surface of the drain layer
112
between adjacent two cells
101
. A gate electrode film
127
of polysilicon is disposed on the gate insulating film
126
.
An interlayer insulating film
141
is disposed on the gate electrode film
127
. The source electrode film
144
and the gate electrode film
127
on each of the cells
101
are insulated from each other by the interlayer insulating film
141
. The source electrode films
144
on the respective cells
101
are interconnected by source electrode films
144
which are disposed on the interlayer insulating films
141
.
A passivation film
150
is disposed on the source electrode films
144
. The passivation film
150
and the interlayer insulating films
141
are patterned to have the source electrode
144
partially exposed on the MOS transistor
105
. Metal films connected to the gate electrode films
127
are also partially exposed on the MOS transistor
105
.
A drain electrode
148
is mounted on the surface of the substrate
111
, i.e., the reverse side of the MOS transistor
105
. The drain electrode
148
, the exposed portions of the source electrode
144
, and the exposed portions of the metal films connected to the gate electrode films
127
are connected to respective external terminals which are connected to an electric circuit for operating the MOS transistor
105
.
For operating the MOS transistor
105
, with the source electrode
144
placed in the ground potential and a positive voltage applied to the drain electrode
148
, when a gate voltage (positive voltage) higher than a threshold voltage is applied to the gate electrode films
127
, an N-type inverted layer is formed on the surface of the P-type channel region
110
and interconnects the source region
161
and the drain layer
112
, causing a current to flow from the drain electrode
148
to the source electrode
144
.
When a voltage (e.g., the ground potential) lower than the threshold voltage is applied to the gate electrode films
127
, the inverted layer is eliminated, reversely biasing the base region
154
and the drain layer
112
. Therefore, no current flows between the drain electrode
148
and the source electrode
144
.
The current path between the drain electrode
148
and the source electrode
144
can be rendered conductive and nonconductive when the voltage applied to the gate electrode films
127
is controlled. Therefore, the MOS transistor
105
is widely used as a high-speed switch in power supply circuits and electric circuits of high power requirements such as motor control circuits.
The conduction resistance of the MOS transistor
105
while it is being conductive is smaller as the sum of the widths of the channel regions of the cells
101
is larger. Stated otherwise, the greater the sum of the peripheral lengths of the base regions
154
and the source regions
161
, the better the MOS transistor
105
. For this reason, there have been proposed cells of various shapes including the illustrated square-shaped cells
101
, comb-shaped cells, and polygonally shaped cells.
The withstand voltage of the MOS transistor
105
is lowest at the spherical junctions at the four corners of each of the cells
101
. Thus, corner-free circular cells have been proposed in order to increase the withstand voltage and the breakdown voltage.
However, while circular cells provide a withstand voltage closer to the withstand voltage of cylindrical junctions than the withstand voltage of spherical junctions, the circular cells pose a problem in that the conduction resistance of the MOS transistor increases because of reduced peripheral lengths of the base regions
154
and the source regions
161
even if the circular cells are arranged in the same pattern as other cells.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a field-effect transistor having a high withstand voltage, a reduced capacitance, and a low conduction resistance.
To achieve the above object, there is provided in accordance with the present invention a field-effect transistor comprising a drain layer being disposed on a surface of substrate, a plurality of base regions having a conductivity type which is opposite to the conductivity type of the drain layer, the base regions being disposed in a surface of the drain layer in an active region, a source region having a conductivity type which is the same as the conductivity type of the drain layer, and at least one source region being disposed in the base regions in surfaces thereof respectively, the base regions having respective outer peripheries spaced from outer peripheries of the source regions disposed respectively in the base regions, the base regions having portions positioned between the outer peripheries of the base regions and the outer peripheries of the source regions, the portions serving as channel regions, respectively, a gate insulating film disposed on a surface of each of the channel regions, and a gate electrode film disposed on a surface of the gate insulating film, the arrangement being such that when a voltage of a predetermined polarity is applied to the gate electrode film to invert the surface of each of the channel regions into a polarity opposite to the base regions, the source regions and the drain layer are connected to each other by the inverted surface of each of the channel regions, each of the base regions having at least one rectangular branch and at least two circular nodes, the base region of the nodes having ends connected to opposite ends of the base region of the branch, the source region in the branch and the source region in the nodes being connected to each other.
The field-effect transistor relating to the present invention, further comprising a plurality of ohmic regions disposed respectively in the base regions, the ohmic regions having a conductivity type which is the same as the conductivity type of the base regions and having a concentration hi
Kunori Shinji
Ohshima Kousuke
Armstrong Westerman & Hattori, LLP.
Loke Steven
Owens Douglas W.
Shindengen Electric Manufacturing Co. Ltd.
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