Field effect transistor

Adhesive bonding and miscellaneous chemical manufacture – Delaminating processes adapted for specified product – Delaminating in preparation for post processing recycling step

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Details

156651, 156652, 156662, 357 41, 357 56, 437 41, 437126, 437228, H01L 2980, H01L 2702, H01L 21306, B44C 122

Patent

active

047558580

ABSTRACT:
The gate of a gallium indium arsenide FET grown on an indium phosphide substrate comprises a top layer of GaInAsP (band gap 1.2 eV) a middle layer of GaInAs and a bottom layer of InP. This can be etched to produce an overhanging top layer which allows self-aligned gate contact metallization avoiding the registration problems of a further masking stage.

REFERENCES:
patent: 4075652 (1978-02-01), Umebachi et al.
patent: 4354898 (1982-10-01), Coldren et al.
patent: 4468850 (1984-09-01), Liau et al.
patent: 4496403 (1985-01-01), Turley
patent: 4636829 (1987-01-01), Greenwood et al.

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