Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-03-09
2003-07-29
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S330000, C257S332000, C257S342000, C257S343000
Reexamination Certificate
active
06600194
ABSTRACT:
This invention relates to field-effect semiconductor devices, particularly but not exclusively insulated-gate field-effect power transistors (so-called MOSFETs) of trench-gate type, comprising side-by-side device cells at one major surface of the body, and at least one drain connection that extends in a drain trench from the one major surface to an underlying drain region. The invention also relates to methods of manufacturing such devices.
U.S. Pat. No. 5,682,048 discloses such a field-effect semiconductor device in the context of allowing a plurality of MOSFETs to be integrated in and on the same device body. Each MOSFET comprises a plurality of side-by-side device cells at one major surface of the body. The configuration of each device cell is conventional in having a source region that is separated by a channel-accommodating region of a first conductivity type from an underlying drain region of an opposite, second conductivity type. In conventional manner, a gate electrode is capacitively coupled to the channel-accommodating region to control a conduction channel between the source and drain regions. The whole contents of U.S. Pat. No. 5,682,048 are hereby incorporated herein as reference material.
In the devices of U.S. Pat. No. 5,682,048, the drain region of each MOSFET comprises an individual highly-doped buried layer between a drain drift region and the device substrate. The individual buried layers allow separate drain connections to the individual MOSFETs. Because a plurality of these MOSFETs are integrated in the same device body, each MOSFET has at least one individual drain connection between the one major surface and the drain buried layer. U.S. Pat. No. 5,682,048 discloses forming these drain connections as low resistivity material in a drain trench that extends through an area of the drain drift region, from the one major surface to the underlying drain buried layer. These trenched drain connections are of much lower resistivity than the drain drift region, and so reduce the ON resistance of the MOSFET.
It is an aim of the present invention to provide trenched drain connections in MOSFETs and similar devices, in a particularly advantageous manner that allows a more compact cellular layout. In addition, a configuration is desirable that may be used advantageously to reduce ON resistance by avoiding a substrate conduction path in discrete devices and to allow proportionally more of the total cellular layout area to accommodate conduction channels.
According to the present invention, there is provided a field-effect semiconductor device comprising a plurality of side-by-side device cells and at least one trenched drain connection, wherein the device has a channel-accommodating region that extends laterally to the drain trench, the drain trench extends through the thickness of the channel-accommodating region to the underlying drain region, and the drain connection is separated from the channel-accommodating region by an intermediate insulating layer on side-walls of the drain trench.
A compact cellular layout can be achieved, because no intermediate area of drain drift region is needed to separate the trenched drain connection from the channel-accommodating region. The invention provides a configuration of trenched drain connection that may even be used in low-voltage devices that do not have a low-doped drift region.
In a discrete device, the underlying drain region may comprise a monocrystalline substrate of the second conductivity type. The trenched drain connection to the upper surface of the body (typically an epitaxial layer) avoids the need to provide a conduction path in conventional manner through the substrate to its lower surface. As device design becomes more efficient in reducing the ON resistance, especially in trench-gate devices, this conduction path in the substrate would add noticeably (in the absence of the invention) to the total ON resistance between source and drain.
In order to accommodate conduction channels in proportionally more of the total cellular layout area, the drain trench may extend through a cell comprising an active source region. This source region can be laterally separated from the drain trench by an intermediate part of the channel-accommodating region.
In order to reduce the total cellular area occupied by the trenched drain connection(s), a drain trench or even each drain trench may extend through a connection cell that is laterally adjoined by device cells without a drain trench. These adjoining device cells may, for example, laterally surround the connection cell.
Several particularly advantageous features and options available with the invention are set out in the appended claims.
Several of the device structures can also be manufactured advantageously in accordance with the invention. Thus, for example, etching the drain trench through the thickness of the channel-accommodating region localises the layout of the channel-accommodating region at the major surface of the body. The channel-accommodating region may be formed from a continuous doped layer of the first conductivity type at this major surface. Thus, for example, it may be formed from a non-localised (blanket) dopant implantation and/or diffusion in at least the active area of the device, or a doped epitaxial layer. When the device is of the trench-gate type, the gate trench may be etched in the same process steps as the drain trench. Both trenches may even be of the same depth.
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Hijzen Erwin A.
Hueting Raymond J. E.
Van Dalen Rob
Biren Steve R.
Koninklijke Philips Electronics , N.V.
Loke Steven
Vu Quang
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