Field effect semiconductor device

Details Field effect semiconductor device Field effect semiconductor device

1999-02-16

2001-03-27

Prenty, Mark V. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S341000, C257S342000

Reexamination Certificate

active

06207993

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a field effect semiconductor device, and more particularly to a field effect semiconductor device having a metal-oxide-semiconductor (MOS) structure in a semiconductor layer which is one of its constituents.
2. Description of the Background Art
A MOS semiconductor device is often used for a switching element because of its operation driven by voltage and relatively easy high-speed switching.
FIGS. 15 and 16
show an example of a prior-art power MOSFET which is one of MOS semiconductor devices.
FIG. 15
is a view showing a pattern of impurities formed in a surface of a semiconductor layer when viewed from its front-surface side of the power MOSFET, and
FIG. 16
is a schematic section taken along the line A—A of FIG.
15
. In
FIG. 15
, a gate electrode
6
, an interlayer insulating film
7
and a source electrode
8
of
FIG. 16
are omitted.
In the power MOSFET having the above structure, an n
−
semiconductor region
2
is formed in an n
+
semiconductor substrate
1
. The n
−
semiconductor region
2
is a constituent of the semiconductor layer. The n
−
semiconductor region
2
is, for example, an epitaxial layer. A plurality of p-type diffusion regions
3
are arranged like islands in a surface of the n
−
semiconductor region
2
, in other words, a one-side major surface of the semiconductor layer. The P-type diffusion region
3
has a planar shape of substantial square and a section of reverse-dome shape (downward convex) with flat bottom. Inside a surface of the p-type diffusion region
3
, an n
+
source region
4
is formed. The n
+
source region
4
has a planar shape of rectangular ring and a substantially rectangular section. The n
+
source region
4
is covered with the p-type diffusion region
3
on the side of the semiconductor layer in order to serve as an FET. A gate insulating film
5
is so formed as to cover the surface of the p-type diffusion region
3
between the n
+
source region
4
and the n
−
semiconductor region
2
and the surface of the n
−
semiconductor region
2
. In other words, the gate insulating film
5
is formed on the one-side major surface of the semiconductor layer above a channel region
10
between the annular peripheral portion of the annular n
+
source region
4
and the peripheral portion of the p-type diffusion region
3
which are adjacent to each other. On the gate insulating film
5
formed is the gate electrode
6
having almost the same planar shape as the gate insulating film
5
. As a material of the gate electrode
6
, for example, polysilicon is used. The interlayer insulating film
7
is so formed as to cover the gate electrode
6
. The surface of the p-type diffusion region
3
inside the annular n
+
source region
4
and a portion of the surface of internal circumference side of the n
+
source region
4
are not covered with the interlayer insulating film
7
. Since the source electrode
8
is deposited entirely on the one-side major surface of the semiconductor layer including above the interlayer insulating film
7
, the source electrode
8
is in contact with the portion of the n
+
source region
4
which is not covered with the interlayer insulating film
7
and the p-type diffusion region
3
surrounded by the n
+
source region
4
on the one-side major surface of the semiconductor layer
100
.
In the power MOSFET having the above structure, when a positive gate voltage is applied to the gate electrode
6
while applying a drain voltage such that the potential of the drain electrode
9
may become positive relative to the potential of the source electrode
8
, the polarity of the surface of the p-type diffusion region
3
between the n
+
source region
4
and the n
−
semiconductor region
2
is reversed into n type, creating a channel in the channel region
10
. In this state, an electronic current flows through the n
+
source region
4
and the channel region
10
into the n
−
semiconductor region
2
, to bring the power MOSFET into conduction.
An on-resistance of this power MOSFET is classified into, for example, resistance elements as shown in FIG.
17
. Reference signs given to the resistance elements of
FIG. 17
are also used to represent values of the resistance elements. In
FIG. 17
, Rn
+
represents the resistance element of the n
+
source region
4
, Rch represents a channel resistance element, Rac represents an accumulation resistance element of the silicon surface, Rj represents the resistance element of a junction FET (J-FET, thereafter) formed between the p-type diffusion regions
3
of adjacent MOS unit cells, Repi represents the resistance element of the n
−
semiconductor region
2
and Rsub represents the resistance element of the n
+
semiconductor substrate
1
. The MOS unit cell refers to a structure including only one p-type diffusion region
3
existing like an island to serve as a MOSFET. When the on-resistance of the power MOSFET is represented as Ron, the on-resistance Ron is obtained from Formula 1:
Ron=Rn
+
+Rch+Rac+Rj+Repi+Rsub  (1)
In order to reduce the on-resistance of the power MOSFET, it is necessary to lower the resistance elements of Formula 1. To lower the channel resistance element Rch, it is effective to increase a channel width. To increase the channel width, it is effective to increase the cell density of the MOS unit cell with size reduction of the p-type diffusion region
3
.
FIG. 18
is a schematic section showing a prior-art vertical MOSFET shown in, for example, Japanese Patent Application Laid Open Gazette 3-70387. To lower the resistance element Rj of the J-FET formed between the p-type diffusion regions
3
, as shown in
FIG. 18
, it is effective to form an n
+
diffusion region 12 between the p-type diffusion regions. The prior-art n
+
diffusion region
12
is formed on the periphery of a region in which a plurality of MOS unit cells are disposed. Providing the n
+
diffusion region
12
produces an effect of reducing the spacing between the p-type diffusion regions
3
without increasing the resistance element Rj, by which the channel resistance element Rch can be lowered.
FIG. 17
also shows an equivalent circuit model of the MOS unit cell. Elements constituting the equivalent circuit model will be described below with reference to
FIG. 17. A
parasitic npn transistor exists therein, consisting of the n
+
source region
4
, the p-type diffusion region
3
and the n
−
semiconductor region
2
. The base of the parasitic npn transistor is connected to the source electrode
8
through a diffusion base resistance Rb. The emitter of the parasitic npn transistor is connected to the source electrode
8
through the resistance element Rn
+
of the source region
4
. The resistance element Rn
+
of the source region
4
, together with the channel resistance element Rch, the accumulated resistance element Rac, the resistance element Rj of the J-FET, the resistance element Repi of the n
−
semiconductor region
2
and the resistance element Rsub of the semiconductor substrate
1
which are connected in series to the resistance element Rn
+
, constitutes the resistance element Ron of the power MOSFET. Representing a potential difference between the n
+
source region
4
and the p-type diffusion region
3
, an avalanche current and a diffusion base resistance immediately below the n
+
source region
4
as Vb, Jb and Rb, respectively, when the condition of Formula 2 is satisfied, the n
+
source region
4
and the p-type diffusion region
3
are brought into a forward bias state, to bring the parasitic npn transistor into conduction.
Vb=Jb×Rb≧about 0.6V  (2)
To turn off the power MOSFET, it is necessary to bring the gate electrode
6
into the same potential as that of the source electrode
8
or a negative

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