Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
1999-06-09
2002-08-06
Dharia, Rupal (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S314000, C710S039000, C710S005000, C710S052000, C711S113000, C711S164000, C711S137000, C711S173000, C370S403000
Reexamination Certificate
active
06430645
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to mapping between a fibre channel (FC) interface and small computer system interface (SCSI) for multiple initiator support and in particular to provide an improved and more efficient mapping scheme to map between FC and SCSI interfaces and improved interfaced communications between hosts and devices, particularly when multiple initiators exist.
2. Description of the Related Art
Fibre channel (FC) technology has been developed and continued to be increased in use as an interface technology. FC interface technology is quickly replacing SCSI interface technology, particularly for interfaces between open servers and disk/tape storage systems. Presently, many disk/tape storage systems do not provide a FC attachment or interface. In order to resolve this problem, IBM has developed the Storage Area Network (SAN) data gateway. The IBM® SAN data gateway is a hardware solution that enables communication between SCSI devices, such as SCSI targets, and FC devices, such as FC hosts. The IBM® SAN data gateway is described in detail in the following references: IBM Storage Area Network Data Gateway General Description Sheet (2 pages), by IBM Storage Systems Division, San Jose, Calif., February 1999; IBM SAN Data Gateway Installation and User's Guide 2108 Model G07, First Edition, by IBM Storage Systems Division, San Jose, Calif., pp. 1-83, March 1999; IBM 2108 Model G07 SAN Data Gateway Technical Course Book, First Edition, by IBM, pp. 1-65, March 1999. These references are incorporated by reference herein.
FIG. 1
shows a general diagram of a prior art SAN data gateway multi-host topology
10
that allows FC and SCSI interface communications. The SAN data gateway or bridge box
20
generally has a FC chip
22
on the FC side of the gateway
20
and a SCSI chip
24
on the SCSI side of the gateway
20
. The FC chip
22
and SCSI chip
24
are coupled together forming a bridge with respect to communications between FC and SCSI. The FC chip
22
and SCSI chip
24
in communications with each other provide the address mapping between the hosts
16
and
18
and the targets
32
and
34
.
FIG. 1
further shows that the hosts
16
and
18
are coupled to the FC chip
22
at the FC side of the SAN data gateway
20
. On the SCSI side of the gateway
20
, Target
1
(target
36
) is coupled from its port
32
through gateway port
28
and to the SCSI chip
24
while Target
2
(which is target
38
) is coupled from its port
34
through gateway port
30
and to the SCSI chip
24
.
For the prior art configuration shown in
FIG. 1
, problems exist when mapping of the multiple FC hosts
16
and
18
occurs on the FC side of a FC to a SCSI converter bridge of the gateway
20
into a single address (Address
1
or address
21
) on the SCSI side of the SCSI converter bridge box or gateway
20
to Target
1
(target
36
) or into a single address (Address
2
or address
23
) on the SCSI side of the SCSI converter bridge box or gateway
20
to Target
2
(target
38
). The multiple host configuration of
FIG. 1
allows the hosts
16
and
18
to be able to respectively issue commands to the targets
36
and
38
at the same time. The present configuration only allows one FC host on the FC side to access and use at one time one SCSI target through each port in order to perform work or various tasks.
For example, in
FIG. 1
, if FC host
16
has reserved SCSI Target
36
or if FC host
16
has issued SCSI commands that take a long time (when sharing is done without a formal device reservation), then the SCSI Host Address
1
(or address
21
) is tied up by the interface communications between FC host
16
and SCSI target
36
only. Since the single Address
1
(or address
21
) is tied up, other commands from FC host
16
or commands from FC host
18
to the target
36
cannot yet be processed and have to be queued and processed in sequence after the Address
1
(or address
21
) is no longer tied up and is finally freed up. The queuing of commands results in command timeouts. Each SCSI target
36
and
38
has a different command timeout for different commands. If one command takes a long time in execution while another command has a short timeout period (such as a “Request Sense”) and the long command comes into the SCSI chip
24
to be processed before the short command, then the short command will not be able to be processed and will be timed out well before the long command is even done processing. A similar problem exists between FC host
18
and Target
2
(target
38
) when Address
2
(address
23
) is used and tied up by FC host
18
and Target
2
(target
38
) when commands are processed therebetween.
It would therefore be advantageous and desirable to provide an improved and efficient address mapping scheme between FC and SCSI, particularly when multiple initiators are supported. It would also be advantageous and desirable to allow other commands to be processed through a FC and SCSI bridge box or gateway when a single command is being processed between a FC host and a SCSI target. It would further be advantageous and desirable to reduce command processing wait time through a FC and SCSI bridge box or gateway. It would still be further advantageous and desirable to avoid or minimize queuing of commands and prevent command timeouts of commands through a FC and SCSI bridge box or gateway.
SUMMARY OF THE INVENTION
It is therefore one object of the present invention to provide an improved and efficient address mapping scheme between FC and SCSI, particularly when multiple initiators are supported.
It is another object of the present invention to allow other commands to be processed through a FC and SCSI bridge box or gateway when a single command is being processed between a FC host and a SCSI target.
It is a further object of the present invention to reduce command processing wait time through a FC and SCSI bridge box or gateway.
It is still a further object of the present invention to avoid or minimize queuing of commands and prevent command timeouts of commands through a FC and SCSI bridge box or gateway.
The foregoing objects are achieved as is now described. An improved and more efficient mapping scheme between a fibre channel (FC) interface and small computer system interface (SCSI) for multiple initiator support. The present mapping scheme provides improved and more efficient mapping between FC and SCSI interfaces and provides improved interfaced communications between hosts and devices, particularly when multiple initiators exist. The present FC and SCSI mapping scheme allows other commands to be processed through a FC and SCSI bridge box or gateway
20
while a single command is being processed therebetween. The present mapping scheme and configuration reduce command processing wait time through a FC and SCSI bridge box or gateway
20
. The present mapping scheme and configuration also avoid or minimize queuing of commands and prevent command timeouts of commands through a FC and SCSI bridge box or gateway
20
. The basic concept of the present invention is to provide at least another alternate mapping path for processing other commands from a FC host to a SCSI target while a single command is being processed therebetween through the normal mapping path. The alternate mapping path may be provided by designating another command pin(s) on the SCSI chip in the gateway or bridge box as an additional mapping address(es) or may be provided by using and coupling additional port(s) on each of the targets having multiple ports wherein the additional port(s) is/are associated with an additional mapping address(es).
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 5430849 (1995-07-01), Banks
patent: 5640541 (1997-06-01), Bartram et al.
patent: 5941972 (1999-08-01), Hoese et al.
patent: 5954796 (1999-09-01), McCarty et al.
patent: 6014383 (2000-01-01), McCarty
patent: 6138161 (2
Dharia Rupal
Millett Douglas R.
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