Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2005-05-10
2005-05-10
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
06891235
ABSTRACT:
An FET has a T-shaped gate. The FET has a halo diffusion self-aligned to the bottom portion of the T and an extension diffusion self aligned to the top portion. The halo is thereby separated from the extension implant, and this provides significant advantages. The top and bottom portions of the T-shaped gate can be formed of layers of two different materials, such as germanium and silicon. The two layers are patterned together. Then exposed edges of the bottom layer are selectively chemically reacted and the reaction products are etched away to provide the notch. In another embodiment, the gate is formed of a single gate conductor. A metal is conformally deposited along sidewalls, recess etched to expose a top portion of the sidewalls, and heated to form silicide along bottom portions. The silicide is etched to provide the notch.
REFERENCES:
patent: 4570328 (1986-02-01), Price et al.
patent: 5356821 (1994-10-01), Naruse et al.
patent: 5650342 (1997-07-01), Satoh et al.
patent: 5650343 (1997-07-01), Luning et al.
patent: 5750430 (1998-05-01), Son
patent: 5937319 (1999-08-01), Xiang et al.
patent: 5981383 (1999-11-01), Lur et al.
patent: 5990532 (1999-11-01), Gardner
patent: 5998289 (1999-12-01), Sagnes
patent: 6015724 (2000-01-01), Yamazaki
patent: 6037630 (2000-03-01), Igarashi et al.
patent: 6087248 (2000-07-01), Rodder
patent: 6124177 (2000-09-01), Lin et al.
patent: 6284613 (2001-09-01), Subrahmanyam et al.
patent: 6306710 (2001-10-01), Long et al.
patent: 6528848 (2003-03-01), Hoshino et al.
patent: 6608356 (2003-08-01), Kohyama et al.
patent: WO 0057461 (2000-09-01), None
patent: 10294453 (1997-04-01), None
“100 nm Gate Length High Performances / Low Power CMOS Transistor Structure” T. Ghani et al., 1999 IEEE, 0-7803-5413-Mar. 1999, IEDM 99 pp. 415-418.
“Well-controlled selectively under-etched Si/SiGe gates for RF and high performance CMOS” T. Skotnicki et al., 2000 Symposium on VLSI Technology Digest of Technical Papers, 2000 IEEE, pp. 156-157.
PCT International Search Report.
Furukawa Toshiharu
Hakey Mark Charles
Holmes Steven John
Horak David Vaclav
Nowak Edward Joseph
Canale Anthony J.
Flynn Nathan J.
Quinto Kevin
LandOfFree
FET with T-shaped gate does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with FET with T-shaped gate, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and FET with T-shaped gate will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3433929