FET Memory with refresh

Details FET Memory with refresh FET Memory with refresh

1981-10-29

1984-02-07

Fears, Terrell W.

Static information storage and retrieval

Systems using particular element

Capacitors

365189, G11C 1124

Patent

active

044307306

ABSTRACT:
Depletion-mode FET (13a of 8) joins to enhancement-mode FET (13b of 8) to store charge capacitively as a memory cell. That enhancement-mode FET (13b of 8) is connected to an FET capacitor (19). When the memory stores a high charge, a refresh clock pulse on a line (21), passes the capacitor (19), turns off enhancement-mode part of joined FETs (8), and is effective to gate refresh switch (25) on. When the memory stores ground, the capacitor (19) is not activated and does not pass the refresh pulses. The memory requires very low power for refresh, and is compact and practical for use in large arrays.

REFERENCES:
patent: 3691537 (1972-09-01), Burgess et al.
patent: 4030083 (1977-06-01), Boll
patent: 4070653 (1978-01-01), Rao et al.
patent: 4112510 (1978-09-01), Baker
patent: 4292677 (1981-09-01), Boll

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