FET Memory with drift reversal

Details FET Memory with drift reversal FET Memory with drift reversal

1981-10-29

1985-08-06

Moffitt, James W.

Static information storage and retrieval

Systems using particular element

Capacitors

365178, 365222, G11C 1124

Patent

active

045340170

ABSTRACT:
In response to a periodic pulse on a lead (21) an FET (47) connected gate-to-drain is driven in a low current circuit, producing a threshold potential on node F. This is connected through switch FETs (61) to the word lines (1) of a memory. This holds the gates of memory access switches (5) at threshold. A higher voltage on the bit line (7) takes off charge in memory cells (40) which have drifted from zero charge stored toward the substrate voltage. Absence of the periodic signal activates an FET (59) which grounds node F. High voltage applied to a word line (1) switches off the FET (61) connecting that line to node F.

REFERENCES:
patent: 4204277 (1980-05-01), Kinoshita
patent: 4291392 (1981-09-01), Proebsting

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