FET memory device

Details FET memory device FET memory device

1991-12-23

1994-08-30

LaRoche, Eugene R.

Static information storage and retrieval

Systems using particular element

Semiconductive

365185, 365218, G11C 1134, G11C 700

Patent

active

053434234

ABSTRACT:
A plurality of trap-type memory transistors are formed in separate wells of a semiconductor substrate, and arranged to constitute a memory matrix. Each well contains the memory transistors belonging to one column of the memory matrix. Each of gate control lines is connected to gate electrodes of the memory transistors belonging to the same row of the memory matrix. One of the memory transistors is selected for writing by separately applying control voltages to the respective wells from an X-decoder, and separately applying control voltages to the respective gate control lines from an Y-decoder. The well and gate control line associated with the memory transistor to be selected are supplied with different voltages than those for the remaining wells and gate control lines.

REFERENCES:
patent: 4375087 (1983-02-01), Wanlass
patent: 4763177 (1988-08-01), Paterson
patent: 4797804 (1989-01-01), Rockett, Jr.
patent: 4996668 (1991-02-01), Paterson et al.
patent: 5051795 (1991-09-01), Gill et al.

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