FET input/output pad layout

Details FET input/output pad layout FET input/output pad layout

1997-07-08

1999-09-07

Hardy, David B.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257786, H01L 2978

Patent

active

059491060

ABSTRACT:
A power FET for which it is difficult to generate oscillations dependent on the interval between adjacent pads. The power FET has a plurality of pads for first terminals, which are disposed on one side of a chip at unequal intervals, and a plurality of pads for second terminals, which are placed on the other side of the chip. Alternatively, or in addition, the plurality of pads for the second terminals may also be disposed at unequal intervals.

REFERENCES:
patent: 4753820 (1988-06-01), Cusack
patent: 4875138 (1989-10-01), Cusack
patent: 4974053 (1990-11-01), Kinoshita et al.
patent: 5757082 (1998-05-01), Shibata
patent: 5796171 (1998-08-01), Koc et al.

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