Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-01-17
2004-05-18
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S390000
Reexamination Certificate
active
06737714
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-011989, filed Jan. 21, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device including a FET having a gate electrode of a honeycomb structure.
2. Description of the Related Art
A FET having a gate electrode of a honeycomb structure has been considered for use as a high frequency element.
A MOSFET of a honeycomb structure has been disclosed, as in IEEE Trans. on Semiconductor Manufacturing, Vol. 13, pp. 167-172, May 2000, for example. The literature is a report about a MOSFET of hexagonal honeycomb structure. In the literature, it is described that a highly integrated (small area) circuit can be provided particularly by a 2-input drain/source common circuit configuration (
FIG. 3
, FIG.
6
). The structure of a conventional MOSFET of honeycomb structure is shown in FIG.
1
.
In the structure shown in the literature, elongated hexagonal gate electrodes are sequentially connected from upper left to lower right. In such a structure, a gate resistance becomes larger, and high frequency characteristics are deteriorated. Further, since a drain diffusion layer contact is obliquely arranged at 45°, and a source electrode wiring is configured with an oblique wiring at 60°, it is predicted that the oblique wiring rule would become highly complicated, resulting in a lower semiconductor device yield.
A conventional FET having a gate electrode of a honeycomb structure has a problem that the wiring design rule of the drain wiring layer and the source wiring layer becomes complicated.
BRIEF SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device capable of simplifying a design rule of drain wiring layers in a convention FET having a gate electrode of a honeycomb structure, as described above.
In order to achieve the above object, according to one aspect of the present invention, there is provided a semiconductor device comprising:
a plurality of unit cells, each comprising a gate insulating film formed on a semiconductor substrate,
a gate electrode formed on the gate insulating film and in which a plurality of hexagonal rings are mutually connected so as to form a honeycomb structure,
a drain diffusion layer formed in the semiconductor substrate on the inside of one hexagonal ring,
and source diffusion layers formed in the semiconductor substrate on the inside of a plurality of hexagonal rings which are adjacent to the hexagonal ring having the drain diffusion layer formed therein;
source contact plugs formed in the semiconductor substrate and are electrically connected to source diffusion layers;
a source wiring layer formed on the semiconductor substrate and is connected to the source contact plugs;
drain contact plugs formed on the semiconductor substrate and are electrically connected to drain diffusion layers; and
a drain wiring layer formed on the semiconductor substrate and being electrically connected to the drain contact plugs,
wherein each unit cell being arranged sharing source diffusion layers in adjacent unit cells,
the hexagonal rings each having two vertexes having an inner angle 90°, and four vertexes having an inner angle 135°, the hexagonal rings each being symmetrical with respect to a segment connecting the two vertexes having an inner angle 90°, and
the drain wiring layer is configured in which a plurality of isosceles triangle rings, where a hypotenuse is parallel to the segment, are mutually connected so as to form a honeycomb structure.
According to another aspect of the present invention, there is provided a semiconductor device comprising:
a plurality of unit cells each comprising a gate insulating film formed on a semiconductor substrate,
a gate electrode formed on the gate insulating film and in which a plurality of hexagonal rings are mutually connected so as to form a honeycomb structure,
a drain diffusion layer formed in the semiconductor substrate on the inside of one hexagonal ring, and
source diffusion layers formed in the semiconductor substrate on the inside of a plurality of hexagonal rings which are adjacent to the hexagonal ring having the drain diffusion layer formed therein;
source contact plugs formed in the semiconductor substrate and are electrically connected to source diffusion layers;
a source wiring layer formed on the semiconductor substrate and is connected to the source contact plugs;
drain contact plugs formed on the semiconductor substrate and are electrically connected to drain diffusion layers; and
a drain wiring layer formed on the semiconductor substrate and is electrically connected to the drain contact plugs,
wherein each unit cell being arranged sharing source diffusion layers in adjacent unit cells,
the hexagonal ring being equilateral hexagonal, and
the drain wiring layer being configured in which a plurality of isosceles triangles are mutually connected so as to form a honeycomb structure.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.
REFERENCES:
patent: 5635742 (1997-06-01), Hoshi et al.
patent: 5838050 (1998-11-01), Ker et al.
patent: 5852315 (1998-12-01), Ker et al.
patent: 6320223 (2001-11-01), Hueting et al.
Matsuzawa, Akira, “A Potential of CMOS as an Ultra-High Speed and High Frequency LSI,”Technical Report of IEICE ED97-50:69-76, Jun. 1997.
Van den Bosch, A., et al., “A High-Density, Matched Hexagonal Transistor Structure in Standard CMOS Technology for High-Speed Applications,”IEEE Transactions on Semiconductor Manufacturing13 (2):167-172, May 2000.
Hara Kazuyoshi
Masuda Hiroo
Christensen O'Connor Johnson & Kindness PLLC
Ngo Ngan V.
Semiconductor Technology Academic Research Center
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