Fet device with double spacer

Details Fet device with double spacer Fet device with double spacer

1996-04-25

1997-09-02

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257340, 257344, H01L 2978

Patent

active

056635869

ABSTRACT:
An improved FET device in which the hot carrier immunity and current driving capability are improved, and the subthreshold leakage current is minimized. The device has a gate electrode with vertical sidewalls, and a thin layer of SiO.sub.2 over the electrode. A first polysilicon spacer is provided on the vertical sidewalls, with a second overlying oxide spacer over the first spacer. The top portion of the SiO.sub.2 layer between the gate electrode and the polysilicon spacer is made conductive enough to keep the gate electrode and the polysilicon spacer at the same potential. Lightly doped source and drain regions are provided.

REFERENCES:
patent: 5073514 (1991-12-01), Ito et al.
patent: 5089432 (1992-02-01), Yoo
patent: 5091763 (1992-02-01), Sanchez
patent: 5108939 (1992-04-01), Manley et al.
patent: 5200351 (1993-04-01), Hadjizadeh-Amini
patent: 5278441 (1994-01-01), Kang et al.
IEDM "Dielectric LDD . . . Effects" (1989)26.1.1 Mizuno et al.

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