FET circuit block with reduced self-heating

Details FET circuit block with reduced self-heating FET circuit block with reduced self-heating

2002-12-20

2004-05-25

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S197000, C257S579000, C257S586000, C257S587000, C257S593000, C257S728000, C257S745000

Reexamination Certificate

active

06740914

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally directed towards reducing deleterious self-heating of FETs in a circuit block of an IC. More particularly, the present invention is directed towards advantageously improving the thermal characteristics of FETs in selected circuit blocks of a microprocessor, such as the control circuits of a silicon-on-insulator (SOI) microprocessor.
2. Description of Background Art
High-speed microprocessors are of interest for a variety of applications. Conventionally, reductions in transistor gate dimensions have been associated with improvements in device performance. The transistors of a a high frequency microprocessor typically have a gate length less than 0.2 microns. For example, advances in device processing, such as deep ultraviolet lithography, permit the gate length of the transistors of a digital logic circuit to be decreased to less than 0.15 microns, thereby improving the maximum cycle rate of digital logic circuits.
Additionally, the use of materials structures that reduce parasitic effects have been associated with increases in transistor speed. In particular, high frequency microprocessors increasingly use a silicon-on-insulator (SOI) field effect transistor (FET) structure. Conventional SOI logic circuits are typically capable of operating at clock cycles up to 20-35% faster than microprocessors fabricated on bulk silicon having comparable gate dimensions.
FIG. 1
shows a cross-section of a conventional SOI transistor
100
. A buried oxide layer
105
is formed on a silicon substrate
102
. A shallow trench isolation (STI) region
110
is formed on both ends of a silicon layer
115
. Conventional semiconductor fabrication techniques are used to form a source diffusion region
120
and a drain diffusion region
125
defining a channel region
130
whose conductivity is controlled by a gate
135
.
Conventionally, the temperature rise (“self-heating”) of the channel of each FET of a microprocessor is typically assumed to have an insignificant effect in regards to the overall performance of the integrated circuit. However, there is increasing interest in the microprocessor industry in fabricating high frequency microprocessors operating at a clock cycle frequency of greater than one gigahertz. However, in order to operate a microprocessor at a high clock cycle frequency, the gate length of the transistors needs to be reduced to below about 0.15 microns. This increases the thermal resistance of each FET, since the thermal resistance of a FET tends to increase inversely with decreases in channel area. Moreover, the use of transistor structures having thermally insulating layers increases the thermal resistance of a FET. In particular, SOI transistors tend to have a high thermal resistance because of the extra thermal resistance created by the buried oxide layer
105
underneath the channel and the STI regions
110
, which blocks the flow of heat from the channel. Silicon dioxide has a thermal conductivity of 1.4 W/(mK), which is over a factor of 60 lower than the thermal conductivity of silicon, which is 85 W/(mK). Consequently, buried oxide layer
105
significantly increases the thermal resistance of the FET.
Therefore, there is a need for an improved technique to reduce self-heating of the transistors in a circuit block of a high frequency integrated circuit, particularly a circuit having SOI FETs.
SUMMARY OF THE INVENTION
A field effect transistor structure having reduced self-heating and its application in selected circuit blocks of an integrated circuit is disclosed. A field effect transistor of the present invention has a semiconductor layer disposed on a substrate, a drain diffusion region formed in the semiconductor layer, a source diffusion region formed in the semiconductor layer, and a gate structure defining a channel region between the drain diffusion region and the source diffusion region. One of the diffusion regions has an area greater than an area associated with the channel region and forms a thermal transfer region for the lateral flow of heat from the channel through the thermal transfer region to the substrate. A heat spreader is disposed on the surface of the semiconductor layer of the thermal transfer region. In one embodiment, the heat spreader includes metal contact layers and interconnects configured to spread heat across the thermal transfer region. The thermal transfer region and heat spreader reduce the thermal resistance and operating temperature of the channel region. In one embodiment the thermal transfer region and heat spreader are configured to reduce the thermal resistance of the channel regions by at least a factor of two. In one embodiment, the field effect transistor of the present invention is used in a circuit block having a circuit output with characteristics that degrade with increasing self-heating, thereby improving the characteristics of the output.
In one embodiment, a circuit block of an integrated circuit incorporates the field effect transistors of the present invention. In a microprocessor application, the integrated circuit includes a processor block having a digital logic circuit with transistor gate length consistent a desired clock cycle frequency. A regulatory circuit block provides a regulatory output for the integrated circuit to be operable at the clock cycle frequency. The regulatory output has characteristics that degrade with self-heating. Field effect transistors in the regulatory circuit that are susceptible to self-heating effects utilize the field effect transistor structure of the present invention, thereby reducing self-heating effects in the regulatory circuit block that may degrade the output characteristics of the regulatory circuit block.
The features and advantages described in the specification are not all inclusive and, in particular, many additional features and advantages will be apparent to one of ordinary skill in the art in view of the drawings, specification, and claims. Moreover, it should be noted that the language used in the specification has been principally selected for readability and instructional purposes, and may not have been selected to delineate or circumscribe the inventive subject matter.


REFERENCES:
patent: 5734193 (1998-03-01), Bayraktaroglu et al.
John A Kowaleski Jr. et al., Implementation Of An Alpha Microprocessor In SOI; Paper 14 2, 4 pages, 2003 Digest of Technical Papers, 2003 IEEE International Solid-State Circuits Conference, Feb. 9-13, 2003, vol. Forty-Six, ISSN 0193-6530, Session 14, Microprocessors.

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