FET and/or bipolar devices formed in thin vertical silicon on in

Details FET and/or bipolar devices formed in thin vertical silicon on in FET and/or bipolar devices formed in thin vertical silicon on in

1996-09-12

1998-03-03

Niebling, John

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

438268, H01L 2184

Patent

active

057233705

ABSTRACT:
A process for fabricating Ultra Large Scale Integrated (ULSI) circuits in Silicon On Insulator (SOI) technology in which the device structures, which can be bipolar, FET, or a combination, are formed in vertical silicon sidewalls having insulation under and in back thereof so as to create SKI device structures. The silicon sidewall device SOI structures, when fabricated, take the form of cells with each cell having a plurality of either bipolar devices, FET devices, or a combination of these devices, such as collectors, emitters, bases, sources, drains, and gates interconnected within the planes of the regions of the devices in the cells and can be interconnected within the planes of the regions of devices in adjacent cells. Further, the interconnections to adjacent cells can be made from the back of the silicon sidewalls.

REFERENCES:
patent: 4753896 (1988-06-01), Matloubian
patent: 4982266 (1991-01-01), Chatterjee
patent: 5312782 (1994-05-01), Miyazawa
patent: 5545586 (1996-08-01), Koh

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