Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-03-22
2004-05-18
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S300000, C257S906000, C257S306000, C365S145000
Reexamination Certificate
active
06737690
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a ferroelectric memory, and more specifically to a simple matrix-type ferroelectric memory that uses only a ferroelectric capacitor and does not have a cell transistor. The present invention further relates to an electronic apparatus equipped with this ferroelectric memory.
2. Description of Related Art
Ferroelectric memory has undergone rapid development in recent years as a form of nonvolatile memory employing a ferroelectric substance. Typically, a ferroelectric capacitor is formed by employing an oxidized ferroelectric material as the capacitor insulating film, and is used as a non-volatile memory by storing data according to the polarization direction of the ferroelectric capacitor.
In the usual ferroelectric memory, the peripheral circuit for selectively carrying out the writing and reading out of data to and from a memory cell and the memory cell are formed in close proximity to one another. A single cell therefore has a large area, making it difficult to improve the degree of integration in the memory cell and increase the memory capacity.
In order to achieve greater integration and higher capacity, a ferroelectric memory was therefore proposed in which a memory cell array is formed that is composed of first signal electrodes having of strip-type electrodes disposed in parallel, second signal electrodes disposed in parallel and in a direction which is perpendicular to the direction of the rows of first signal electrodes, and a ferroelectric layer disposed in between the aforementioned first and second signal electrodes at the areas of intersection therebetween, wherein the memory cells in this memory cell array are arranged in the form of a matrix (see Japanese Patent Application, First Publication No. Hei 9-128960).
When a voltage is impressed on a given selected cell in a ferroelectric memory composed of this type of memory cell array, however, a voltage is also impressed on non-selected cells. In order to minimize this effect, a method has been proposed in which a voltage Va is impressed on the selected cell and a voltage Va/3 or −Va/3 is impressed on non-selected cells, this method being accomplished by impressing, for example, a voltage Va on the selected first signal electrode, a voltage Va/3 on the nonselected first signal electrodes, a voltage 0 on the selected second signal electrode, and a voltage 2Va/3 on the non-selected second signal electrodes (see Japanese Patent Application, First Publication No. Hei 9-128960). Accordingly, a domain inversion must occur at Va but must not occur at Va/3 in the ferroelectric layer. In other words, the polarization-electric field (P-E) hysteresis curve must have angularity.
In the usual ferroelectric memory design, the memory cell portion is formed on top of a SiO
2
protecting layer that is formed on the peripheral circuit that contains the MOS transistor. It is therefore not possible to control the orientation of the ferroelectric layer, and so, the angles that are formed by the impressed electric fields and the polarization axes of each crystal grain vary from one another. As a result, variation also arises in the voltage impressed when each crystal grain undergoes domain inversion, which leads to problematic deterioration in the angularity of the hysteresis curve.
BRIEF SUMMARY OF THE INVENTION
Hereafter, also in the embodiments and claims, numerals accompanied by the parenthesis like (
010
) or (
100
) indicate the condition of orientation such as disposing direction of the single crystal or the like.
It is therefore the objective of the present invention to provide a ferroelectric memory which is provided with both integration and memory characteristics by improving the angularity of the ferroelectric layer's hysteresis curve, this objective being accomplished by employing a structure in which the memory cell array and the peripheral circuit are disposed in a plane separated from one another, and the memory cell array is subjected to epitaxial growth on a Si single crystal. It is a further objective of the present invention to provide an electronic apparatus equipped with this ferroelectric memory.
The ferroelectric memory is characterized by a structure in which:
a memory cell array is disposed on a Si single crystal substrate, the memory cell array consisting of first signal electrodes and second signal electrodes disposed facing and perpendicular to each other, and a ferroelectric layer held in between the first signal electrodes and the second signal electrodes, wherein the regions of intersection between the first signal electrodes and the second signal electrodes that include the ferroelectric layer are disposed in the form of a matrix for employment as memory cells; and
a peripheral circuit that includes a MOS transistor for selecting the memory cells is disposed on the Si single crystal substrate in a plane separated from the memory cell array;
and wherein the first signal electrodes undergo epitaxial growth on the Si single crystal substrate via a buffer layer, and the ferroelectric layer undergoes epitaxial growth on the first signal electrodes.
By exploiting the fact that the memory cell array and the peripheral circuit are disposed in a plane separated from one another in the above structure, the memory cells can be made to undergo epitaxial growth directly on the Si single crystal. As a result, it is possible to realize a ferroelectric memory in which there is improved angularity in the ferroelectric layer's hysteresis curve, and which is provided with both integration and memory characteristics.
The ferroelectric memory is also characterized in that, in the above ferroelectric memory the ferroelectric layer is composed of an oxidized ferroelectric material having a perovskite structure, or an oxidized ferroelectric material having a Bi layered perovskite structure.
The above structure is effective in obtaining a ferroelectric memory provided with both integration and memory characteristics by employing an oxidized ferroelectric material having a perovskite structure or an oxidized ferroelectric material having a Bi layered perovskite structure, by means of which impressive developments in memory characteristics have been achieved in recent years.
The ferroelectric memory is also characterized in that, in the above the ferroelectric memory the Si single crystal substrate is a (
100
) substrate; the buffer layer includes one of either titanium nitride (TiN) or a metal oxide MO (M=Mg, Ca, Sr, Ba) which has NaCl structure and are (
100
)-oriented or (
110
)-oriented in cubic system; and the first signal electrodes include one of either metal platinum Pt which is (
100
)-oriented in cubic system or a conductive oxide which has a perovskite structure and are (
100
)-oriented in cubic system or (
100
)-oriented in pseudo-cubic system.
By making the first signal electrodes which is (
100
)-oriented in cubic system or in pseudo-cubic system undergo epitaxial growth on the (
100
) Si single crystal substate, the above structure has the effect of causing the ferroelectric layer to undergo epitaxial growth on to the first signal electrodes.
The ferroelectric memory is also characterized in that, in the above ferroelectric memory the ferroelectric layer has a polarization moment in the (
001
) direction in tetragonal system, and is composed of an oxidized ferroelectric material having a (
001
)-oriented perovskite structure.
By means of the above structure, a ferroelectric layer containing a representative ferroelectric substance, PZT (PbZr
x
Ti
1−x
O
3
), can be made to undergo epitaxial growth at a (
001
) orientation in tetragonal system on a (
100
) Si single crystal substrate, which has the effect of providing a ferroelectric memory having good angularity.
The ferroelectric memory is also characterized in that, in the above ferroelectric memory the Si single crystal substrate is a (
10
) substrate; the buffer layer includes one of either titanium nitride (TiN) or a metal oxide MO (M=Mg, Ca
Hasegawa Kazumasa
Higuchi Takamitsu
Iwashita Setsuya
Miyazawa Hiromu
Natori Eiji
Harness & Dickey & Pierce P.L.C.
Jackson Jerome
Seiko Epson Corporation
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