Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2002-09-19
2004-03-30
Nguyen, VanThu (Department: 2824)
Static information storage and retrieval
Systems using particular element
Ferroelectric
Reexamination Certificate
active
06714435
ABSTRACT:
FIELD OF THE INVENTION
The invention disclosed relates generally to memory cells, and more particularly to ferroelectric nonvolatile memory cells.
BACKGROUND OF THE INVENTION
Ferroelectric transistors are structurally identical to metal-oxide-silicon field effect transistor (MOSFET) devices with the gate oxide layer replaced by a ferroelectric material layer
12
, as shown in FIG.
1
. The polarization state of the ferroelectric material layer
12
gives rise to an electric field, which shifts the turn-on threshold voltage of the device
10
. Transistors known in the prior art often include a non-ferroelectric dielectric layer
16
between the ferroelectric material and the silicon substrate
18
, as shown in the device
14
of FIG.
2
. This dielectric layer
16
generally has several purposes at the silicon/ferroelectric interface including avoidance of uncontrolled growth of silicon dioxide, avoidance of high electric fields at the interface, separating the ferroelectric materials from the silicon, avoidance of crystal lattice structure mismatch between the silicon and the ferroelectric materials, and keeping hydrogen away from the ferroelectric materials. Such a dielectric layer
16
is sometimes also placed between the top electrode layer
20
and the ferroelectric layer
12
for the same reasons. These devices, such as devices
10
and
14
and variants thereof, are utilized in arrays of rows and columns to form one-transistor (“1T”) non-volatile ferroelectric memories.
When a voltage greater than a coercive voltage is applied across the ferroelectric material, the ferroelectric material polarizes in the direction aligning with the electric field. When the applied voltage is removed, the polarization state is preserved. When a voltage greater than the coercive voltage is applied to the ferroelectric material in the opposite direction, the polarization in the ferroelectric material reverses. When that electric field is removed, the reversed polarization state remains in the material. The electric field generated by the polarization offsets the natural turn-on threshold of the transistors, effectively shifting the turn-on thresholds of the transistors. By applying known voltages less than the coercive voltage on the terminals of the transistor, the state of the polarization within the ferroelectric material can be detected without altering the stored polarization states, a method known in the prior art as non-destructive read-out.
These devices are generally electrically connected in an array of rows and columns with common row signals and column signals to form a memory array. A common figure of merit to establish manufacturing costs of these memory arrays is the area utilized per data bit. When utilized in an array of this type, many prior art configurations require additional transistors to provide for the selection of a single device within the array.
What is desired, therefore, is a minimum area ferroelectric non-volatile memory cell structure and a method of biasing such that a single one-transistor memory cell capable of storing two data bits can be written to and accessed without disturbing other cells within an array.
SUMMARY OF THE INVENTION
According to principles of the present invention, a novel apparatus and method of storing and accessing two bits in a single ferroelectric FET (field effect transistor) exhibiting hysteresis, each FET having gate, source, and drain, terminals and a substrate is disclosed. Ferroelectric material sandwiched between the substrate and the gate terminal in the region of the source is polarized in one of two states to form a first data bit within the FET. Ferroelectric material sandwiched between the substrate and the gate terminal in the region of the drain is polarized in one of two states to form a second data bit within the FET. Non-ferroelectric dielectric is sandwiched between the substrate and the gate terminals in regions between the ferroelectric material in the source region and the ferroelectric material in the drain region. The polarization of the ferroelectric material in the source region changes the threshold voltage of the FET regardless of the polarization state in the drain region. Accordingly, the detection of the first data bit, determined by the polarization state of the material in the source region, is accomplished by applying a read bias to the FET terminals, a first current resulting when a first state is stored and a second current resulting when a second state is stored. The polarization of the second data bit is accomplished by reversing the source and drain voltages. The FETs are electrically connected in an array of rows and columns, the gates of the FETs in a common row connected by a common word line, the sources of the FETs in a common column sharing a common bit line, the drains of the FETs in a common column sharing a common bit line, and the substrate of all FETs sharing a common substrate. Appropriate write voltage biasing of the word lines, bit lines, and substrate provides means for polarizing a single ferroelectric region of a single FET within the array, while leaving the polarization of all other ferroelectric regions unchanged. Appropriate read voltage biasing of the word lines, bit lines, and substrate provides means for detection of the polarization state of a single ferroelectric region of a single FET within the array, a first bit line current determining a first state and a second bit line current determining a second state.
The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment of the invention, which proceeds with reference to the accompanying drawings.
REFERENCES:
patent: 3832700 (1974-08-01), Wu et al.
patent: 4860254 (1989-08-01), Pott et al.
patent: 5046043 (1991-09-01), Miller et al.
patent: 5060191 (1991-10-01), Nagasaki et al.
patent: 5070385 (1991-12-01), Evans, Jr. et al.
patent: 5146299 (1992-09-01), Lampe et al.
patent: 5198994 (1993-03-01), Natori
patent: 5227855 (1993-07-01), Momose
patent: 5302842 (1994-04-01), Chan
patent: 5307305 (1994-04-01), Takasu
patent: 5345414 (1994-09-01), Nakamura
patent: 5365094 (1994-11-01), Takasu
patent: 5378905 (1995-01-01), Nakamura
patent: 5384729 (1995-01-01), Sameshima
patent: 5418389 (1995-05-01), Watanabe
patent: 5434811 (1995-07-01), Evans, Jr. et al.
patent: 5479317 (1995-12-01), Ramesh
patent: 5515311 (1996-05-01), Mihara
patent: 5519235 (1996-05-01), Ramesh
patent: 5523964 (1996-06-01), McMillan et al.
patent: 5536672 (1996-07-01), Miller et al.
patent: 5541870 (1996-07-01), Mihara et al.
patent: 5541871 (1996-07-01), Nishimura et al.
patent: 5541873 (1996-07-01), Nishimura et al.
patent: 5559733 (1996-09-01), McMillan et al.
patent: 5563081 (1996-10-01), Ozawa
patent: 5578846 (1996-11-01), Evans, Jr. et al.
patent: 5621681 (1997-04-01), Moon
patent: 5623439 (1997-04-01), Gotoh et al.
patent: 5640030 (1997-06-01), Kenney
patent: 5736759 (1998-04-01), Haushalter
patent: 5739563 (1998-04-01), Kawakubo et al.
patent: 5744374 (1998-04-01), Moon
patent: 5757042 (1998-05-01), Evans, Jr. et al.
patent: 5768185 (1998-06-01), Nakamura et al.
patent: 5780886 (1998-07-01), Yamanobe et al.
patent: 5789775 (1998-08-01), Evans, Jr. et al.
patent: 5808676 (1998-09-01), Biegelsen et al.
patent: 5822239 (1998-10-01), Ishihara et al.
patent: 5825317 (1998-10-01), Anderson et al.
patent: 5858533 (1999-01-01), Greuter et al.
patent: 5872739 (1999-02-01), Womack
patent: 5877977 (1999-03-01), Essaian
patent: 5886920 (1999-03-01), Marshall et al.
patent: 5887117 (1999-03-01), Desu et al.
patent: 5919515 (1999-07-01), Yano et al.
patent: 5946224 (1999-08-01), Nishimura
patent: 5953061 (1999-09-01), Biegelsen et al.
patent: 5955213 (1999-09-01), Yano et al.
patent: 5959879 (1999-09-01), Koo
patent: 5962884 (1999-10-01), Hsu et al.
patent: 5977577 (1999-11-01), Evans, Jr.
patent: 5998819 (1999-12-01), Yokoyama et al.
patent: 6025735 (2000-02-01), Gardner et al.
patent: 6027947 (2000-02-01), Evans et al.
patent: 6031754 (2000-02-01),
Dimmler Klaus
Gnadinger Alfred P.
Cova Technologies, Inc.
Hogan & Hartson LLP
Kubida William J.
Meza Peter J.
Nguyen Van-Thu
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