Ferroelectric transistor and memory cell configuration with...

Details Ferroelectric transistor and memory cell configuration with... Ferroelectric transistor and memory cell configuration with...

2002-04-01

2003-09-02

Whitehead, Jr., Carl (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S316000, C257S319000, C257S296000

Reexamination Certificate

active

06614066

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The invention lies in the fields of integrated technology, semiconductor technology, and memory technology.
Ferroelectric materials have been investigated for some time with respect to their suitability for storage applications, that is for memory applications. Here, two variants are primarily being considered. Firstly, ferroelectric material can be used as a dielectric layer with a high dielectric constant in a capacitor of a DRAM memory cell configuration. Secondly, ferroelectric transistors have been proposed (see, for example, European patent EP 0 566 585 B1; H. N. Lee et al, Ext. Abstr. Int. Conf. SSDM, Hamatsu, 1997, pp. 382-83; I. P. Han et al, Integrated Ferroelectrics, 1998, Vol. 22, pp. 213-21), which have two source-drain regions, a channel region and a gate electrode, a layer of ferroelectric material being provided between the gate electrode and the channel region. The conductivity of these transistors depends on the state of polarization of the layer of ferroelectric material. Ferroelectric transistors of this type are suitable for use in nonvolatile memories. In this case, two different logic values of an item of digital information are associated with two different states of polarization of the layer of ferroelectric material. Further possible uses for such ferroelectric transistors are, for example, neural networks.
Since ferroelectric material which is arranged on the surface of a semiconductor substrate exhibits poor boundary surface properties, which exert a negative influence on the electrical properties of a ferroelectric transistor, it has been proposed to use an intermediate layer of SiO
3
(See EP 0 566 585 B1), MgO, CeO
2
, ZrO
2
, SrTiO
3
, Y
2
O
3
(See H. N. Lee et al, Ext. Abstr. Int. Conf. SSDM, Hamatsu, 1997, pp. 382-383) or Si
3
N
4
(see, for example I. P. Han et al, Integrated Ferroelectrics, 1998, Vol. 22, pp 213-221) between the ferroelectric layer and the semiconductor substrate in a ferroelectric transistor. These materials are insulating, stable oxides, which produce a sufficiently good boundary surface between the ferroelectric layer and the surface of the semiconductor substrate.
Between the gate electrode and the semiconductor substrate acting as an electrode, the ferroelectric layer is polarized. As a result of the remanent polarization, an electric field is generated. If a value of about 10 &mgr;c/cm
2
is assumed for the remanent polarization of the ferroelectric layer, then, for an intermediate layer of SiO
2
with ∈
r
=3.9, a value of about 29 MV/cm is calculated for the electric field strength. The electric field strength is calculated in accordance with the formula E=&sgr;/(∈
0
·∈
r
), where E is the electric field strength and &sgr; is the remanent polarization. Since the breakdown field strength of SiO
2
is only around 10 MV/cm, electric breakdown of the intermediate layer must therefore be expected. The values for the remanent polarization, in particular of SBT (SrBi
2
Ta
2
O
9
) or PZT (PbZr
x
Pi
1−x
O
2
), lie above 10 &mgr;C/cm
2
, and even when using a dielectric material with a higher dielectric content than SiO
2
, it is therefore necessary to expect that field strengths in a critical range will occur.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a ferroelectric transistor and its utilization in a memory cell configuration, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which provides for a ferroelectric transistor wherein breakdown of a dielectric layer between a ferroelectric layer and a semiconductor substrate is avoided.
With the foregoing and other objects in view there is provided, in accordance with the invention, a ferroelectric transistor, comprising:
a substrate having a main surface;
a first source-drain region, a channel region, and a second source-drain region adjoining said main surface of said semiconductor substrate, with said channel region arranged between said first and second source-drain regions;
a dielectric layer covering at least said channel region and overlapping said first source-drain region;
a ferroelectric layer disposed on said dielectric layer and covering at least a part of said first source-drain region adjacent said channel region;
a first polarization electrode and a second polarization electrode disposed on said dielectric layer, with said ferroelectric layer arranged between said first and second polarization electrodes;
a gate electrode above a first area of said channel region;
said dielectric layer having a thickness above said first area less than a thickness above a second area of said channel region below said second polarization electrode; and
said dielectric layer having a thickness above said part of said first source-drain region adjoining said channel region dimensioned such that a remanent polarization of said ferroelectric layer, aligned parallel to said main surface of said substrate, produces compensation charges in said second area of said channel region.
The ferroelectric transistor is particularly suitable for use as a memory cell in a memory cell configuration.
The ferroelectric transistor comprises a first source-drain region, a channel region and a second source-drain region, which adjoin a main surface of a semiconductor substrate. Here, the channel region is arranged between the first source-drain region and the second source-drain region. A dielectric layer is provided, which covers at least the surface of the channel region and overlaps the surface of the first source-drain region. Arranged on the surface of the dielectric layer is a ferroelectric layer, which covers at least a part, adjacent to the channel region, of the first source-drain region.
Also arranged on the surface of the dielectric layer are a first polarization electrode and a second polarization electrode, between which the ferroelectric layer is arranged. A gate electrode is arranged on the surface of the dielectric layer, above an area of the first channel region.
The thickness of the dielectric layer above the first area, that is to say under the gate electrode, is lower than above a second area of the channel region, which is arranged under the second polarization electrode. The thickness of the dielectric layer above that part of the first source-drain region which adjoins the channel region and is covered by the ferroelectric layer is dimensioned such that a remanent polarization of the ferroelectric layer, which is aligned parallel to the main surface, produces compensation charges in the second area of the channel region.
Since a remanent polarization of the ferroelectric layer is aligned parallel to the main surface in the ferroelectric transistor, because of the first polarization electrode and the second polarization electrode, the electric field generated by the remanent polarization is likewise aligned parallel to the main surface. The compensation charges in the second area of the channel region are generated by the lateral stray field from the electric field, which is much lower than the electric field itself. Therefore, breakdown of the dielectric layer between the semiconductor substrate and the ferroelectric layer is reliably avoided.
Depending on the state of polarization of the ferroelectric layer, a different number of compensation charges is generated in the second area of the channel region. In order to store an item of digital information, the ferroelectric layer is switched into two different polarization states, one polarization state generating so many compensation charges in the second area that the second area conducts, while the other polarization state generates so few compensation charges that the second area of the channel region does not conduct. The ferroelectric transistor is controlled via the gate electrode, which controls the first area of the channel region. A check is made to see whether the ferroelectric transistor conducts, in this case the polarization of the

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