Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-03-14
2003-09-30
Nguyen, Cuong Quang (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S306000
Reexamination Certificate
active
06627930
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates, in general, to the field of integrated circuit (“IC”) devices incorporating ferroelectric capacitors. More particularly, the present invention relates to integrated circuit devices incorporating one or more ferroelectric thin film capacitors and a method for producing the same wherein the capacitor dielectric includes multi-layered crystallographic textures.
Ferroelectric memory devices, such as the FRAM® (FRAM® is a registered trademark of Ramtron International Corporation, Colorado Springs, Colo.) family of solid state, random access memory integrated circuits provide non-volatile data storage through the use of a ferroelectric dielectric material which may be polarized in one direction or another in order to store a binary value. The ferroelectric effect allows for the retention of a stable polarization in the absence of an applied electric field due to the alignment of internal dipoles within the Perovskite crystals in the dielectric material. This alignment may be selectively achieved by application of an electric field that exceeds the coercive field of the material. Conversely, reversal of the applied field reverses the internal dipoles.
Data stored in a ferroelectric memory cell is “read” by applying an electric field to the cell capacitor. If the field is applied in a direction to switch the internal dipoles, more charge will be moved than if the dipoles are not reversed. As a result, sense amplifiers can measure the charge applied to the cell bit lines and provide an indication of a stored logic “1” or “0” at the IC output pins. In a conventional two transistor/two capacitor (“2C/2T”) ferroelectric memory cell for example, a pair of two data storage elements are utilized, each polarized in opposite directions. To “read” the state of a 2T/2C memory cell, both elements are polarized in the same direction and the sense amps measure the difference between the amount of charge transferred from the cells to a pair of complementary bit lines. In either case, since a “read” to a ferroelectric memory is a destructive operation, the correct data is then restored to the cell during a precharge operation.
In a simple “write” operation, an electric field is applied to the cell capacitor to polarize it to the desired state. Briefly, the conventional write mechanism for a 2T/2C memory cell includes inverting the dipoles on one cell capacitor and holding the electrode, or plate, to a positive potential greater than the coercive voltage for a nominal 100 nanosecond (‘nsec.”) time period. The electrode is then brought back to circuit ground for the other cell capacitor to be written for an additional nominal 100 nsec.
Certain ferroelectric dielectrics, such as lead zirconate titanate (PZT, a proprietary formulation of Ramtron International Corporation) may be produced with a variety of crystallographic textures, including <100>, <111>, <001> and random textures. For example, polycrystalline PZT films having the {100} crystal planes parallel to the substrate surface are said to be <100> textured. Films composed of crystallites that, on average, have no specific crystallographic orientation relative to the substrate surface are said to be randomly oriented.
Previously, it has been demonstrated that thin films can be produced with mixtures of textured PZT crystallites, however, it could not be unambiguously determined just how the textured crystallites were distributed through the film. Recently, grazing incident angle x-ray diffraction measurement techniques have been developed to determine that crystallites with differing types of crystallographic textures can be concentrated in well-defined layers throughout the thickness of a thin film dielectric.
See for example: Fox, G. R., “X-Ray Diffraction Method for Determining Textured Volume Fractions in PZT Thin Films”. The position and thickness of PZT layers with differing textures strongly influences the ferroelectric performance of the PZT films including such properties as Q
sw
(switching polarization); V(90) (voltage at which Q
sw
is 90% of the maximum switched charge); fatigue (the decrease in Q
sw
with the number of switching cycles); retention (the decay of the stored state over time) and imprint (a condition wherein it becomes more difficult to switch to an opposite state from that currently stored).
SUMMARY OF THE INVENTION
In accordance with the principles of the present invention, many different types of thin film capacitor ferroelectric dielectric structures based on multi-layers of differing texture may be provided.
Generally, the main body (or bulk) of the film may consist of a ferroelectric dielectric (e.g. PZT) that is crystallographically oriented such that the spontaneous polarization of some component of the spontaneous polarization is aligned with the direction of the applied field (e.g. <111>, <001> or RND). In this way, the bulk of the film can be switched ferroelectrically. Relatively thin layers of ferroelectric dielectric with textures that are different from that of the bulk can be introduced at the interface between the bulk ferroelectric layer and the bottom and/or top electrodes. This interstitial (or interfacial) layer can be textured such that it can (or cannot) be switched ferroelectrically.
The advantages of these structures are that the interface properties can be tailored simply by altering the texture of the ferroelectric layer. The effect of the interface layer(s) is to change the electric field distribution across the bulk and interface due to differences in the dielectric constants of the different textured layers. In addition, charge trapping and domain pinning can be altered using the differing polarization states of the textured layers.
The technique of the present invention relates to the use of ferroelectric dielectrics such as PZT, strontium bismuth tantalate (SBT) or other Perovskite ferroelectric materials, whether lead based, strontium based or otherwise and regardless of whether the ferroelectric dielectric is utilized for its non-volatile storage characteristics or because of its enhanced dielectric characteristics in conventional capacitor applications such as in the memory cells of dynamic random access memory (“DRAM”) memory cells.
In a exemplary embodiment disclosed herein utilizing PZT, an integrated circuit capacitor is formed comprising a dielectric having multiple layers of PZT with different crystallographic textures to produce a multi-layered thin film device with improved performance for non-volatile ferroelectric random access memory devices. The multi-layered crystallographic textured capacitors disclosed herein provide much enhanced performance and operating characteristics over conventional ferroelectric devices incorporating dielectric layers having but a single crystallographic texture.
Particularly disclosed herein is an integrated circuit device including at least one capacitor having a top and bottom electrode thereof and a ferroelectric dielectric layer therebetween. The ferroelectric dielectric layer comprises a first ferroelectric layer having a first crystallographic texture forming a main body of the dielectric layer and a second ferroelectric layer having a second differing crystallographic texture forming an interface layer between the main body and one of the top and bottom electrodes.
Also disclosed herein is a method for forming a capacitor comprising the steps of: providing a bottom electrode; forming a first ferroelectric dielectric layer overlying the bottom electrode, the first ferroelectric dielectric layer having a first crystallographic texture; also forming a second ferroelectric dielectric layer overlying the first ferroelectric dielectric layer, the second ferroelectric dielectric layer having a second crystallographic texture different than the first crystallographic texture; and providing a top electrode overlying the second ferroelectric dielectric layer.
REFERENCES:
patent: 6060736 (2000-05-01), Noshiro
patent: 6229166 (2001-05-01), Kim e
Chu Fan
Eastep Brian
Fox Glen
Sun Shan
Fujitsu Limited
Hogan & Hartson L.L.P.
Nguyen Cuong Quang
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