Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2001-05-23
2003-01-28
Elms, Richard (Department: 2824)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S201000, C365S210130
Reexamination Certificate
active
06512686
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a ferroelectric storage device and a test method thereof. More particularly, the present invention relates to a ferroelectric storage device which includes a memory element (memory cell) including a switching transistor and a ferroelectric capacitor and which memorizes information depending on a polarization direction of the ferroelectric capacitor, and a test method thereof.
2. Description of the Related Art
FIG. 13
shows a hysteresis loop exhibiting a characteristic of a ferroelectric capacitor. The horizontal axis indicates a voltage V applied between both electrode ends of the ferroelectric capacitor. The vertical axis indicates the amount of polarization Pr. A ferroelectric memory utilizing the hysteresis characteristic of the ferroelectric capacitor is used as a non-volatile memory, and a variety of its applications are currently proposed.
FIG. 14
shows a structure of a memory cell of a ferroelectric storage device. A memory storage operation of the memory cell will be described with reference to FIG.
13
.
When “H” data is written to the memory cell, a bit line is transitioned to the “H” level and a plate line is transitioned to the “L” level while a word line is transitioned to the “H” level so that a MOS transistor is in the ON state. The polarization state of a ferroelectric capacitor in this situation is indicated by A in FIG.
13
. When the bit line is transitioned to the “L” level, the potential of the ferroelectric capacitor is zero volts, but the polarization remains (this state is indicated by B in FIG.
13
).
When “L” data is written to the memory cell, the bit line is transitioned to the “L” level and the plate line is transitioned to the “H” level while the word line is transitioned to the “H” level so that the MOS transistor is in the ON state. The polarization state of a ferroelectric capacitor in this situation is indicated by D in FIG.
13
. Thereafter, when the plate line is transitioned to the “L” level, the voltage applied to the ferroelectric capacitor is zero volts, but an inverted polarization remains (this state is indicated by E in FIG.
13
).
To read out information, the bit line is transitioned to the “L” level and a pulse of “L” to “H” to “L” is applied to the plate line while the word line is transitioned to the “H” level so that the MOS transistor is in the ON state. In this case, the ferroelectric capacitor in which the “H” data is written is transitioned to B to C to D to E, so that the polarization is inverted. In contrast, the ferroelectric capacitor in which the “L” data is written is transitioned to E to D to E, so that the polarization is not changed.
Thus, in the ferroelectric capacitor, a destructive readout is executed which leads to a change in information in the memory cell due to the readout operation. The change of the polarization causes a change in the amount of electric charge output from the ferroelectric capacitor, which appears as a small difference in potential in the bit line. Such a small difference in potential is amplified by a sense amplifier (not shown) so as to be read out as data.
A ferroelectric capacitor is categorized into the following two types: a ferroelectric memory (hereinafter referred to as a “1T1C-type ferroelectric memory”) in which one memory cell includes one transistor and one ferroelectric capacitor; and a ferroelectric memory (hereinafter referred to as a “2T2C-type ferroelectric memory”) in which one memory cell includes two transistors and two ferroelectric capacitors.
FIG. 7
shows a circuit of a conventional 1T1C-type ferroelectric memory
700
. The 1T1C-type ferroelectric memory
700
includes a memory cell MC which is shown in FIG.
14
. The memory cell MC is connected to a word line WL, a plate line PL, a bit line BIT
0
, and a bit line BIT
1
. The 1T1C-type ferroelectric memory
700
includes a memory cell ref_MC for generating a reference potential which is used as a reference used in determining whether data written in the memory cell MC is the “H” data or the “L” data. The memory cell ref_MC is connected to a reference word line Ref_WL, a reference plate line Ref_PL, bit lines BIT
0
and BIT
1
, and bit lines BIT
0
# and BIT
1
# paired with the respective bit lines BIT
0
and BIT
1
. The reference memory cell ref_MC outputs data having an intermediate level between the “H” data and the “L” data output from the memory cell MC, by short-circuiting an output of the memory cell MC in which the “H” data is written and an output of the memory cell MC in which the “L” data is written.
FIG. 8
is a timing chart used for explaining an operation of the conventional 1T1C-type ferroelectric memory
700
. Initially, using a Row control circuit and a Ref_Cell control circuit, the word line WL and the reference word line Ref_WL are transitioned to the “H” level, and then pulses (readout pulses) are applied to the plate line PL and the reference plate line Ref_PL. In this case, pulses having the same potential are applied to the respective plate line PL and plate line Ref_PL. When, using a Row control circuit and a Ref_Cell control circuit, the word line WL and the reference word line Ref_WL are transitioned to the “H” level, and then pulses (readout pulses) are applied to the plate line PL and the reference plate line Ref_PL, the “H” data or the “L” data is output from the memory cell MC to the bit lines BIT
0
and BIT
1
. Similarly, data having a reference level is output from the reference memory cell Ref_MC to the bit lines BIT
0
# and BIT
1
#. Thereafter, an SAE (Sense Amp. Enable) is transitioned to the “H” level so that the sense amplifier (Sense Amp.) is actuated and the potential difference between both bit lines is amplified.
Such data is read out in reading out information (the operation is hereinafter also referred to as a “READ operation”). To avoid a destructive readout of information from a storage device, a rewrite operation is performed in the memory cell MC using a rewrite pulse. In writing information (the operation is hereinafter referred to as a “WRITE operations”), the difference in potential between both bit lines is amplified, and thereafter write data (data to be written) is transferred to a bit line before the rewrite pulse is applied to the memory cell MC. Thereafter, the data is written to the memory cell MC using the rewrite pulse. When a READ or WRITE operation to the memory cell MC is performed in the 1T1C-type ferroelectric memory
700
, the “L” level of a pulse applied to a plate line is typically zero volts and the “H” level is typically VCC. During the time that the rewrite operation is executed using the rewrite pulse, the reference word line Ref_WL is transitioned to the “L” level so that the reference cell Ref_MC is cut off a bit line, and initial data for generating data having the reference level is written to the reference cell Ref_MC. For example, the reference memory cell ref_MC generates data having the reference level by generating data having an intermediate level between the “H” data and the “L” data output from the memory cell MC. The intermediate-level data is obtained by short-circuiting an output of the memory cell MC in which the “H” data is written and an output of the memory cell MC in which the “L” data is written. In this case, the “H” data and the “L” data are written to difference memory cells in order to cause the reference memory cell ref_MC to generate the reference-level data.
FIG. 9
shows another conventional 1T1C-type ferroelectric memory
900
. The 1T1C-type ferroelectric memory
900
includes a Ref_Level generation circuit in order to generate a reference voltage instead of the reference memory cell ref_MC included in the 1T1C-type ferroelectric memory
700
. The Ref_Level generation circuit divides a resistance between VCC and GND so that data having an intermediate level between the “H” data and the “L” data can be output.
FIG. 10
is a timing chart used for explaining another conventional 1T1C-type ferroelectric memory
900
. In
Elms Richard
Morrison & Foerster / LLP
Nguyen Tuan T.
Sharp Kabushiki Kaisha
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