Ferroelectric storage device

Details Ferroelectric storage device Ferroelectric storage device

2002-09-03

2004-10-05

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S203000

Reexamination Certificate

active

06801447

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a nonvolatile memory and specifically concerns a reading operation of a semiconductor memory having a ferroelectric capacitor.
BACKGROUND OF THE INVENTION
In recent years, nonvolatile memories having a function of retaining data until power is turned off have been realized by using ferroelectric materials such as PZT, which demonstrates hysteresis characteristics. Such ferroelectric materials are used for a memory cell, so that nonvolatile memories are achieved with simple configurations.
Since FeRAM (Ferroelectric Random Access Memory) has nonvolatile characteristics and operates at high speed with low voltage, a number of manufacturers of memory chips have been interested in FeRAM. The operating speed of FeRAM is determined by polarization inversion time. The polarization inversion speed of a ferroelectric capacitor is determined by an area of the capacitor, a thickness of a ferroelectric thin film, applied voltage, and so on, and is normally expressed in nanosecounds [ns].
FIG. 15
shows a hysteresis loop of a ferroelectric capacitor.
A vertical axis indicates a quantity of charge induced on a surface of a ferroelectric by spontaneous polarization of the ferroelectric, that is, a polarization quantity [C]. A horizontal axis indicates voltage [V] applied to the ferroelectric capacitor.
When positive voltage is applied to the ferroelectric in a state in which the ferroelectric capacitor has an inter-terminal voltage of 0 [volt] and polarization does not occur, a polarization quantity increases from S
0
to A of FIG.
15
. The ferroelectric does not increase in polarization quantity at a certain voltage (electric field) or more. Namely, a polarization quantity reaches a maximum quantity at point A. The slope at this point is defined by the equation below.
Cs=dg/dV
where Cs represents a parallel plate capacitance component. Thereafter, even when an inter-terminal voltage of the ferroelectric capacitor is set at 0, a polarization quantity does not change to 0 but remains at S
1
. At this moment, a quantity of held polarization is expressed by Pr [C]. This characteristic is used to realize a nonvolatile memory.
FIG. 13
shows a ferroelectric memory including a typical memory cell of 1T1C (one transistor, one capacitor).
Reference character WL denotes a word line, reference characters BL and XBL denote bit lines, and reference characters BLS and XBLS denote sub bit lines.
Reference numeral
101
denotes a ferroelectric capacitor having one end connected to a cell plate line CP.
Reference numeral
103
denotes a reference capacitor having one end connected to a reference capacitor plate line RCP.
Reference numeral
102
denotes a ferroelectric capacitor selection transistor controlled by the word line WL.
Reference numeral
104
denotes a reference capacitor selection transistor controlled by a reference capacitor selection line RWL (hereinafter, referred to as a RWL line).
Reference numeral
112
denotes a sub bit line charge transistor serving as a sub bit charge circuit. The transistor is controlled by a pre-charge control signal PRE to pre-charge the sub bit lines BLS and XBLS to a level of power supply voltage Vdd.
Reference numeral
111
denotes a transfer gate serving as a bit line charge circuit. The transfer gate is constituted by transistors M
1
and M
2
for connecting the bit lines BL and XBL and the sub bit lines BLS and XBLS, and is controlled by an SSW line.
Reference numeral
113
denotes a sense amplifier which amplifies a potential difference between the bit lines BL and XBL and is controlled by a sense amplifier control signal SEN.
Reference numeral
110
denotes a transistor which discharges the bit lines BL and XBL to a ground potential and is controlled by a bit line discharge control signal BLDIS (hereinafter, referred to as a BLDIS line).
Reference numeral
120
denotes a bit line parasitic capacitance represented as parasitic capacities Cb of the bit lines BL and XBL.
Reference numeral
121
denotes a sub bit line parasitic capacitance represented as parasitic capacities Cbls of the sub bit lines BLS and XBLS.
Reference numeral
122
denotes a reading operation control section.
The reading operation control section
122
is configured so as to have a timing chart of FIG.
14
.
Besides, in the present specification, an activating state will be represented as “H” level.
At time t
0
, the BLSDIS line is inactivated to cause the bit lines BL and XBL to enter a floating state.
At time t
1
, the SSW line is activated, and at time t
2
, the bit lines BL and XBL are pre-charged to the Vdd level. Further, the pre-charge control signal PRE is activated to stop the pre-charging of the bit lines BL and XBL.
At time t
3
, when the word lines WL and RWL are activated at a Vpp level (potential higher than Vdd) and a memory cell is selected, the voltage Vdd is applied to the ferroelectric capacitor
101
and the reference capacitor
103
.
The following equations approximately indicate a potential Vbl (H) of the bit line when the ferroelectric capacitor
101
stores “H” data, and a potential Vbl (L) of the bit line when the ferroelectric capacitor
101
stores “L” data, respectively.
Vbl
(
H
)=
Vdd−{Vdd
/(
Cb/Cs
+1)}
Vbl
(
L
)=
Vdd−{Vdd
/(
Cb/Cs
+1)+(2
Pr/Cs
)/(
Cb/Cs
+1)}
Moreover, the reference capacitor
103
is set such that the reference bit line XBLS has a potential Vxbl expressed by the equation below.
Vxbl=Vdd−{Vvp
/(
Cb/Cs
+1)+(2
Pr/Cs
)/(
Cb/Cs
+1)}/2
Thus, BL=BLS and XBL=XBLS have a potential difference Vdif.
Vdif
=
Vxb1
-
Vb1
=
Pr
/
Cs
/
(
Cb
/
Cs
+
1
)
(
1
)
Subsequently, at time t
4
, the sense amplifier control signal SEN is activated to start the sense amplifier
113
, amplifying a bit line potential difference (|BL−XBL|).
Next, at time t
5
, the cell plate line CP is activated to rewrite “L” data in the ferroelectric capacitor
101
. At time t
6
, the cell plate line CP is inactivated so as to inactivate the sense amplifier control signal SEN. At time t
7
, the BLDIS line is activated to discharge the bit lines BL and XBL. After the bit lines BL and XBL are discharged to VSS, the word line WL is inactivated at time t
8
, and the pre-charge control signal PRE is inactivated at time t
9
to pre-charge the sub bit lines BLS and XBLS. The reading cycle is completed thus.
DISCLOSURE OF THE INVENTION
Equation (1) demonstrates the characteristic of a reading potential which increases as the parasitic capacitance Cb decreases. However, in reality, the bit line brought into a floating state is reduced in potential and sufficient voltage is not applied to the ferroelectric capacitor
101
due to its quantity of polarization charge, so that it is not possible to read all the quantities of charge (polarization charge quantity: 2Pr) accumulated in a ferroelectric.
Further, when the polarization charge quantity 2Pr is increased by providing a larger area of the ferroelectric capacitor
101
and a smaller thickness of the ferroelectric, the parasitic capacitance Cs also increases. Similarly as the above description, voltage applied to the ferroelectric capacitor
101
decreases, voltage (electric field) applied to the ferroelectric is reduced, so that a quantity of polarization charge during writing cannot be retrieved from the memory cell. It is needless to say that lower voltage applied to the ferroelectric during a low-voltage operation is a more serious problem.
The present invention has an object to provide a ferroelectric storage device which can fundamentally solve the above-described problems and perform a reading operation with stability.
The ferroelectric storage device of the present invention comprises reading means for detecting and reading a quantity of charge applied for charging a bit line in bit line charging circuits for charging the bit line connected to a selection transistor, the transistor being connec

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