Ferroelectric semiconductor memory device

Details Ferroelectric semiconductor memory device Ferroelectric semiconductor memory device

1998-05-28

2000-03-14

Mai, Son

Static information storage and retrieval

Systems using particular element

Ferroelectric

365149, G11C 1122

Patent

active

060381604

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

The present invention relates to a semiconductor memory device using a ferroelectric capacitor.


BACKGROUND ART

In a semiconductor memory device, mainly, an electric charge is accumulated in a memory cell capacitor formed within a semiconductor device, and the data is stored depending on presence or absence of the electric charge (generally called dynamic memory or DRAM). In this memory cell capacitor, hitherto, a silicon oxide film was used as a capacity insulation film. Recently, using a ferroelectric material as a capacity insulation film of a memory cell capacitor, a semiconductor memory device for realizing nonvolatility of stored data is proposed.
A semiconductor memory device using a ferroelectric film as a capacity insulation film of a memory cell capacitor is described below.
FIG. 9 is a circuit block diagram of a conventional semiconductor memory device.
In FIG. 9, reference numerals 30a to 30d are memory cells, and 31a to 31d are memory cell transistors. Reference numerals 32, 34 are word lines, and 33a to 33d are memory cell capacitors. Reference numerals 35 to 38 are bit lines, and 39, 40 are cell plate lines. Reference numerals 41, 42 are sense amplifiers, 43 to 46 are bit line precharging transistors, BLP is a bit line precharge control signal, and SAE is a sense amplifier control signal.
As shown in FIG. 9, in a circuit configuration of a conventional semiconductor memory device, the bit line 35 (BL0) and bit line 36 (/BL0) are connected to the sense amplifier 41. Two memory cells 30a, 30b are connected to these bit lines 35, 36.
In the memory cell 30a, two memory cell capacitors 33a and two MOS transistors are provided. These two memory cell capacitors 33a have two electrodes individually. One electrode of the two electrodes of one memory cell capacitor 33a (located at the left side in the drawing) is connected to the bit line 35 through the MOS transistor 31a (located at the left side in the drawing), and the other electrode is connected to the cell plate line 39. The other one of the two electrodes of the memory cell capacitor 33a (located at the right side in the drawing) is connected to the bit line 36 through the MOS transistor 31a (located at the right side in the drawing), and the other electrode is connected to the cell plate line 39. Each gate of the two MOS transistors 31a is connected individually to the word line 32 (word line 0).
The memory cells 30b to 30d are composed same as the memory cell 30a.
The bit lines 35, 36 are connected to the grounding potential (VSS) through the MOS transistors 43, 44 controlled by the bit line precharge control signal BLP.
In the conventional semiconductor memory device shown in FIG. 9, one memory cell 30a is composed of two memory cell capacitors 33a and two MOS transistors 31a. When writing data, one of the two memory cell capacitors 33a is written in logic voltage "H", and the other in logic voltage "L", and when reading out the data, the potential difference being read out from the two memory cell capacitors 33a is amplified by the sense amplifier 41 and the data is read out.
The operation of the ferroelectric memory using a ferroelectric material as a capacity insulating film is described below while referring to FIG. 10 and FIG. 11. FIG. 10 is a diagram for explaining reading of data in the memory cell in the conventional semiconductor memory device, and a hysteresis curve of ferroelectric is shown.
In the capacitor using ferroelectric material as a capacity insulating film, a residual electric field is left over as indicated at point B and point E even if the voltage is 0 as shown in FIG. 10.
Thus, by utilizing the residual electric field left over in the ferroelectric capacitor even after turning off the power source as nonvolatile data, a nonvolatile semiconductor memory device is realized.
That is, when the data of the memory cell 30a is "1," one memory cell capacitor 33a (called first memory cell capacitor) out of two memory cell capacitors 33a is in the state of point B, and the other memory cell capacitor 33a (ca

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