Ferroelectric resistor non-volatile memory array

Details Ferroelectric resistor non-volatile memory array Ferroelectric resistor non-volatile memory array

2003-01-15

2004-11-16

Lam, David (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S148000, C365S065000

Reexamination Certificate

active

06819583

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to ferroelectric non-volatile memory arrays, and specifically to a memory array which features a non-destructive read and which functions similarly to a constant current memory device.
BACKGROUND OF THE INVENTION
One-transistor one-ferroelectric capacitor (1T1C) memory cells and single transistor ferroelectric-based devices are used as memory storage devices. Although the 1T1C memory is non-volatile, it is read destructive, i.e., the stored data is lost during a read operation, requiring refreshment of the cell. A read operation in a single transistor memory is non-destructive, however, because there is a relatively large field across the ferroelectric capacitor during standby conditions, there is a significant reduction in memory retention time.
S. Onishi et al,
A half
-
micron Ferroelectric Memory Cell Technology with Stacked Capacitor Structure
, IEDM, paper 34.4, p. 843, 1994, describes fabrication of a ferroelectric memory cell using dry etching of a PZT/Pt/TiN/Ti structure.
SUMMARY OF THE INVENTION
A ferroelectric thin film resistor memory array is formed on a substrate and includes plural memory cells arranged in an array of rows and columns; wherein each memory cell includes: FE resistor having a pair of terminals, and a transistor associated with each resistor, wherein each transistor has a gate, a drain and a source, and wherein the drain of each transistor is electrically connected to one terminal of its associated resistor; a word line connected to the gate of each transistor in a row; a programming line connected to each memory cell in a column; and a bit line connected to each memory cell in a column. In one embodiment, the programming line is connected to the FE resistor other terminal and the bit line is connected to the transistor source, while in another embodiment, the programming line is connected to the transistor source and the bit line is connected to the FE resistor other terminal. In the latter embodiment, the programming line is suitable for function as a block erase line.
It is an object of the invention to provide a non-destructive read long detention time ferroelectric memory resistor array suitable for embedded as well as stand alone large scale non-volatile memory
Another object of the invention is to provide a memory array which function similarly to a constant current array.
This summary and objectives of the invention are provided to enable quick comprehension of the nature of the invention. A more thorough understanding of the invention may be obtained by reference to the following detailed description of the preferred embodiment of the invention in connection with the drawings.


REFERENCES:
patent: 6404668 (2002-06-01), Kowarik et al.
patent: 6627936 (2003-09-01), Ishii
S. Onishi et al,A half-micron Ferroelectric Memory Cell Technology with Stacked Capacitor Structure, IEDM, paper 34.4, p. 843, 1994.

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