Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2007-11-20
2007-11-20
Phung, Anh (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S145000
Reexamination Certificate
active
11347337
ABSTRACT:
A unit cell is composed of a memory cell transistor and a ferroelectric storage element connected in parallel between a source and a drain of the memory cell transistor. A memory cell block is composed of a plurality of unit cells connected in series. One end of the memory cell block is connected to a bit line via a block selecting transistor. The other end of the memory cell block is connected to a plate line. A redundancy unit cell is composed of a redundancy cell transistor and a ferroelectric storage element connected in parallel between a source and a drain of the redundancy cell transistor. A redundancy memory cell block is composed of a plurality of unit cells connected in series, the number of which is smaller than that of the unit cells in the memory cell block.
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Domae Sumiko
Takashima Daisaburo
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Phung Anh
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