Ferroelectric random access memory

Static information storage and retrieval – Systems using particular element – Ferroelectric

Reexamination Certificate

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Details

C365S230030

Reexamination Certificate

active

11220853

ABSTRACT:
Four memory cells each obtained by connecting a ferroelectric capacitor in parallel to a transistor are connected in series with each other to constitute a cell block. A sense amplifier circuit is arranged on a one-end side in a column direction every four cell blocks sequentially adjacent to each other in a row direction. One ends of the four cell blocks are connected to four different plate lines, respectively, and the other ends of the four cell blocks are connected to four different bit lines through four block selection transistors, respectively. Of the four bit lines, two bit lines constitute a first bit line pair, and the two remaining bit lines constitute a second bit line pair. Any one of the first and second bit line pairs is connected to the sense amplifier circuit and the other bit line pair is connected at a constant voltage.

REFERENCES:
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patent: 6094370 (2000-07-01), Takashima
patent: 6493251 (2002-12-01), Hoya et al.
patent: 6924997 (2005-08-01), Chen et al.
patent: 6950361 (2005-09-01), Kamoshida et al.
patent: 10-255483 (1998-09-01), None
patent: 11-177036 (1999-07-01), None
patent: 2000-22010 (2000-01-01), None
Hideto Hidaka, et al., “Twisted Bit-Line Architectures for Multi-Megabit DRAM's”, IEEE Journal of Solid-State Circuits, vol. 24, No. 1, Feb. 1989, pp. 21-27.
Hiroshige Hirano, et al., “2-V/100-ns 1T/1C Nonvolatile Ferroelectric Memory Architecture with Bitline-Driven Read Scheme and Nonrelaxation Reference Cell”, IEEE Journal of Solid-State Circuits, vol. 32, No. 5, May 1997, pp. 649-654.

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