Ferroelectric random access memory

Details Ferroelectric random access memory Ferroelectric random access memory

2002-03-05

2003-08-26

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S189090

Reexamination Certificate

active

06611450

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-060422, filed Mar. 5, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a ferroelectric random access memory (FeRAM) and more particularly to suppression of the imprint in a FeRAM memory cell.
2. Description of the Related Art
In recent years, the FeRAM has been developed aggressively as a semiconductor storage device for low power consumption and mentioned in, for example, U.S. Pat. No. 4,873,664 (Eaton, Jr), “A Ferroelectric DRAM Cell for High Density NVRAMs”, S. S. Eaton, Jr et al., ISSCC Digest of Technical Papers, pp. 130-131, February 1988.
When electric field is applied to a ferroelectric insulation film used in the FeRAM, polarization of charges is generated, so that the relation between applied voltage and polarization amount indicates so-called hysteresis characteristic.
Conventionally, FeRAM cells of various kinds of configuration have been proposed and recently, 1-transistor/1-capacitor (1T/1C) type FeRAM, in which a cell selecting MOS transistor T is connected to a ferroelectric capacitor C employing ferroelectric film between electrodes, and 2T/2C type FeRAM, in which two cells of 1T/1C FeRAM are used as a pair and so on are available.
FIG. 31
shows an equivalent circuit having 1-transistor/1-capacitor (1T/1C) as an example of the FeRAM cell.
In a memory cell array in which a plurality of the FeRAM cells are arrayed, a drain of a cell selecting MOS transistor Tst of each cell is connected to a bit line BL, a gate of a cell selecting MOS transistor Tst is connected to a word line WL and an end (plate electrode) of a ferroelectric capacitor Cm is connected to a plate line PL.
FIG. 32
is a characteristic diagram showing the relation between applied electric field (applied voltage V) on the ferroelectric film for use in the FeRAM cell and polarization amount P.
The FeRAM cell stores binary data, which is determined depending upon which remnant polarization Pr of the ferroelectric film is positive or negative when no electric field is applied to the ferroelectric film of the ferroelectric capacitor in the FeRAM cell or when applied voltage between capacitor electrodes is V=0, as evident from this hysteresis characteristic.
Here, “positive” or “negative” of the remnant polarization Pr indicates in which way the polarization is directed between the plate electrode of the ferroelectric capacitor and bit line electrode. A state in which the polarization is present in one direction is defined as data “1” while a state in which the polarization is present in the other direction is defined as data “0”.
In order to improve reliability of the above-described FeRAM, increasing rewritable times of the FeRAM cell, holding data for a long hour, improvement of environment resistance, suppression of imprint and the like can be mentioned. One of the measures, which cannot be improved easily is suppression of imprint.
The imprint refers to such phenomenon that if the FeRAM cell is left for a long hour in a state in which data is written therein (with the ferroelectric film polarized) or the ferroelectric film is exposed to high temperatures in a state in which data is written in the FeRAM cell, movable charges are gathered around polarization domain in a direction for stabilizing the polarization, so that internal electric field is generated in the ferroelectric film. Meanwhile, no imprint is generated during ordinary operation of the FeRAM cell.
Because the aforementioned internal electric field, which is generated in the ferroelectric film, is temporary, the imprint is not a phenomenon which causes such a hard error as destruction or aging of devices. However, this cause such a soft error which disables polarization data in an opposite direction to a polarization direction of storage data in the FeRAM cell from being written properly.
A problem about the imprint in the FeRAM will be described in detail.
In manufacturing process of the FeRAM, after a screening test for screening which a chip region is good or bad is carried out on the stage of wafer, the wafer is cut to chips and the respective chips are assembled in the form of a package. Or after a shipment test is carried out with data written into the FeRAM, the FeRAM is soldered to a circuit substrate of an application product. In these cases, a high temperature of 200 to 300° C. is applied to the FeRAM cell in the polarization state. In such a case, the imprint is generated.
FIG. 32
shows hysteresis characteristic with a solid line in case where the direction of remnant polarization Pr in the ferroelectric capacitor is for example in the direction which defines storage of data “1” while indicating hysteresis characteristic with a dotted line in case where the imprint is generated after that. The hysteresis characteristic in case where the imprint is generated is deflected from its center as if bias voltage is applied.
According to the hysteresis characteristic in case where the imprint is generated, the polarization state is accelerated so that it becomes unlikely to be inverted to inverse polarization and the quantity of signals for reading the inverse polarization is reduced, thereby leading to reduction of the characteristic of the FeRAM cell.
When reading data “1” in
FIG. 32
, read potential at a point where a straight line indicating the relation between the capacity C, applied voltage V and charge amount Q of the ferroelectric capacitor intersects the hysteresis characteristic is a when the hysteresis characteristic is expressed in the solid line A and b when the hysteresis characteristic is expressed with the dotted line B. And the read signal amount drops.
As described above, the conventional FeRAM has a problem that the soft error is generated by acceleration of the imprint which occurs because the ferroelectric film is left for a long hour or exposed to high temperatures.
BRIEF SUMMARY OF THE INVENTION
According to an aspect of the present invention, there is provided a ferroelectric random access memory comprising: a cell array including a plurality of memory cells each having a ferroelectric memory device and a cell selecting transistor connected in series to the ferroelectric storage device; and imprint restricting circuit configured to restrict generation of an imprint by setting a polarization amount of a ferroelectric film of the ferroelectric memory device in the memory cell to an amount smaller than a polarization amount generated at a normal write time.
According to another aspect of the present invention, there is provided a ferroelectric random access memory comprising a cell array including a plurality of memory cells each having a ferroelectric memory device and a switching transistor connected in parallet to the ferroelectric storage device; and imprint restricting circuit configured to restrict generation of an imprint by setting a polarization amount of a ferroelectric film of the ferroelectric memory device in the memory cell to an amount smaller than a polarization amount generated at a normal write time.
According to a further aspect of the present invention, there is provided a ferroelectric random access memory comprising: a sense amplifier configured to be connected to a bit line and to amplify data read out to the bit line; a cell block comprising a plurality of memory cells; and a separating transistor inserted in the bit line between the sense amplifier and the cell block, wherein the separating transistor is controlled by a gate control signal at a write time to lower a bit line potential on the cell block side than a bit line potential on the sense amplifier side.


REFERENCES:
patent: 5525528 (1996-06-01), Perino et al.
patent: 5903492 (1999-05-01), Takashima
patent: 5953245 (1999-09-01), Nishimura
patent: 6522567 (2003-02-01), Iwanari
patent: 2000-003948 (2000-01-01), None

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