Ferroelectric nonvolatile transistor

Details Ferroelectric nonvolatile transistor Ferroelectric nonvolatile transistor

2000-01-12

2002-10-08

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S300000, C257S296000

Reexamination Certificate

active

06462366

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to MOS transistors, and specifically to a MOS memory transistor that incorporates a ferroelectric layer.
BACKGROUND OF THE INVENTION
Prior art single transistor ferroelectric devices may be classified in two types of devices: Metal-Ferroelectric-Metal-Oxide Semiconductor (MFMOS) transistors and Metal-Ferroelectric-Metal-Semiconductor (MFMS) transistors. The structures of such devices are depicted in FIG.
1
and
FIG. 2
, respectively.
Referring initially to
FIG. 1
, a MFMOS memory transistor is depicted generally at
10
. Transistor
10
is constructed on a silicon substrate
12
. The transistor includes a gate region
14
, a n+ source region
16
, a n+ drain region
18
and a ferroelectric (FE) gate stack
20
. Gate stack
20
includes a bottom electrode
22
, a FE layer
24
, and a top electrode
26
. An oxide insulating layer
28
covers the conductive portions of the transistor. The completed transistor includes a source electrode
30
, a gate stack electrode
32
, and a drain electrode
34
. As shown in
FIG. 2
, a MFMS memory transistor
36
is similarly constructed to transistor
10
, but includes an n-layer
38
in gate region
14
.
The materials used in the FE stack for the top and bottom electrode in known ferroelectric memory transistors are Pt, Ir, Zr, IrO, ZrO, or alloys containing one or more of the metals. To insure proper operation of the completed device, the gate stack has to be precisely etched to align the sides of the ferroelectric capacitor. Although equipment is available for performing such etching on the metals, the etch, is at best, a sputtering process, which is only partially successful. It is not possible to selectivity etch the metal without damaging the surrounding silicon oxide and silicon to a degree that is acceptable, which requires that gate stack plasma etching consumes the surrounding silicon and oxide in amounts less than several tens of nanometer. Any consumption greater than this amount will degrade or destroy the normal operation of the memory transistor.
SUMMARY OF THE INVENTION
A method of fabricating a ferroelectric memory transistor using a lithographic process having an alignment tolerance of, includes preparing a silicon substrate for construction of a ferroelectric gate unit; implanting boron ions to form a p-well in the substrate; isolating plural device areas on the substrate; forming a FE gate stack surround structure; etching the FE gate stack surround structure to form an opening having a width of L
1
to expose the substrate in a gate region; oxide is deposited by CVD to a thickness of between about 10 nm to 40 nm over the exposed substrate; forming a FE gate stack over the gate region, wherein the FE gate stack has a width of L
2
, wherein L
2
≧L
1
+2&dgr;; depositing a first insulating layer over the structure; implanting arsenic or phosphorous ions to form a source region and a drain region; annealing the structure; depositing, by CVD, a second insulating layer; and metallizing the structure.
A ferroelectric memory transistor includes a silicon substrate having a p-well formed therein; a gate region, a source region and a drain region disposed along the upper surface of said substrate; a FE gate stack surround structure having an opening having a width of L
1
located about said gate region; a FE gate stack formed in said FE gate stack surround structure, wherein said FE gate stack has a width of L
2
, wherein L
2
≧L
1
+2&dgr;, wherein &dgr; is the alignment tolerance of the lithographic process.
An object of the invention is to improve the manufacturing yield of ferroelectric memory transistors.


REFERENCES:
patent: 5384729 (1995-01-01), Sameshima
patent: 5536962 (1996-07-01), Pfiester
patent: 6002150 (1999-12-01), Gardner et al.
patent: 6013584 (2000-01-01), M'Saad
patent: 6159781 (2000-12-01), Pan et al.
Pierret, “Field Effect Devices,” 1990, Addison-Wesley Publishing Company, vol. 4, pp. 138-139.

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