Ferroelectric memory with spare memory cell array and ECC...

Details Ferroelectric memory with spare memory cell array and ECC... Ferroelectric memory with spare memory cell array and ECC...

2007-01-30

2008-08-05

Mai, Son L (Department: 2827)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S189070

Reexamination Certificate

active

07408824

ABSTRACT:
A semiconductor memory comprising a memory cell array, a spare memory cell array, a spare data replacing circuit, a syndrome computing circuit, and an ECC circuit is disclosed. The data in the memory cell replaced with a memory cell in the spare memory cell array is set to 0 and then the syndromes of the data read from the memory cell array are calculated. In parallel with the syndrome calculation, the data in the memory cell of the memory cell array is replaced with the data read from a spare memory cell. Then, the syndromes of the data read from the memory cell in the spare memory cell array are calculated. The calculated syndromes and the output of the spare data replacing circuit are supplied to the ECC circuit, which corrects the error if there is a 1-bit error in the data read from the memory cell array.

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U.S. Appl. No. 11/397,572, filed Apr. 5, 2006, Hoya et al.
U.S. Appl. No. 11/668,706, filed Jan. 30, 2007, Hoya et al.

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