Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2000-03-09
2001-07-03
Nelms, David (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S189011
Reexamination Certificate
active
06256220
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention in general relates to the design and fabrication of ferroelectric memories, and more particularly to memory architecture that includes a shunt between the isolated nodes of adjacent ferroelectric capacitors in the memory cell which prevents undesirable switching of the ferroelectric material.
2. Statement of the Problem
Ferroelectric memories have been known for many years and offer many advantages over other memories. See U.S. Pat. No. 5,561,307, issued Oct. 1, 1996 to Takashi Mihara et al., for example. One of the most common and commercially successful ferroelectric memory designs utilizes a memory cell comprising a ferroelectric capacitor, one electrode of which is connected to a transistor, and the other electrode of which is connected to a line, conventionally called the plate line. The design and operation of a memory of this type is similar to the DRAM, thus these memories are commonly referred to as FeRAMs. There is at least one important difference between a DRAM and an FeRAM: a “read voltage” must be placed across the ferroelectric memory to read it. This difference has resulted in significant difficulties in designing an FeRAM that is as fast, failure resistant and dense as a conventional DRAM. See, for example, U.S. Pat. No. 5,406,510 issued Apr. 11, 1995 to Takashi Mihara et al.
One solution to the need for applying a voltage across the FeRAM to read it, has been to hold the plate line at a fixed (constant) voltage, usually equal to ½ the supply voltage. See U.S. Pat. No. 5,406,510 referenced above as well as U.S. Pat. No. 5,038,323 issued to Leonard J. Schwee on Aug. 6, 1991. In these designs the same plate line is connected to all or at least a portion of all memory cells, and thus is referred to as a common or cell plate line. The plate line is held at a constant voltage, which is ½ the supply voltage, Vcc. A problem with this design is that the electrical node between the capacitor and the transistor, though isolated from the rest of the circuit, tends to lose charge through various leakage paths such that the voltage on the node reaches a level different from that of the plate line. This is essentially a result of the fact that reversed-biased diodes and “off” MOSFETs have significant leakage in comparison to the leakage through the ferroelectric capacitor itself. The zero voltage of the node between the transistor and capacitor, which we will call the TC node herein, and the constant ½ Vcc voltage on the plate line results in a voltage, Vf, being developed across the ferroelectric capacitor at times when it is not being written to or read from, which voltage can cause the ferroelectric capacitor to switch, destroying the data held in the memory.
Another solution to the need to apply a voltage across the FeRAM to read it, is to pulse the common plate line only during certain portions of the read/write cycle. See for example, U.S. Pat. No. 4,873,664 issued Oct. 1989 to S. Sheffield Eaton and Tatsumi Sumi et al., “A 256 kb Nonvolatile Memory at 3V and 100 ns”, in
ISSCC Digest of Technical Papers,
pp. 268-269, February 1994. In both these designs, the common plate line has a relatively large capacitance, and thus relatively large access time and a relatively slow memory. In addition, in the Eaton reference, the memory cell layout requires that adjacent rows of memory cells have unique plate lines, that is, if the plate lines are shared between rows, the deselected rows are sufficiently disturbed during the read or write cycles of adjacent rows, then the information in these shared but deselected rows is destroyed. The unique plate line for each row increases the area required by each row of memory cells. In the Sumi reference, the plate line is shared between two adjacent rows, however, only one of the rows is selected. One electrode of each ferroelectric capacitor in the deselected row receives the plate pulse. Because of a parasitic capacitance of the internal TC node in the cell structure, the internal TC node acts as a small capacitor in series with the large. ferroelectric capacitor. Since the higher voltage drop is across the smaller capacitor in a series of capacitors, a significant voltage is developed on the TC node, which results in a small voltage existing for a relatively long time across each ferroelectric capacitor in the deselected cells, causing a disturb of its data state.
A solution to the above problerhs is to refresh the TC node to the ½ Vcc voltage of the plate line often enough that the voltage on the node never falls below a threshold voltage during periods that it is not being read or written to, which threshold voltage is close enough to the plate voltage to prevent disturbance of the memory state. See Hiroki Koike et al. “A 60-ns 1-Mb Nonvolatile Ferroelectric Memory with Non-Driven Cell Plate Line Write/Read Scheme”, in
ISSCC Digest of Technical Papers,
pp. 368-369, February 1996. This results in a faster access time, but complicates the peripheral circuitry, consuming chip area and reducing the density of the memory. In addition, periods of time during normal memory operation must be set aside for the refresh to take place, thereby restricting memory access and introducing wait states.
Another solution is to connect the TC node to ground and to the bit line when a cell is not selected. See Patent Abstracts of Japan, vol. 096, no. 11, Nov. 29, 1996, and JP 08180671 A (Matsushita Electric Ind. Co. Ltd.), Jul. 12, 1996. However, connecting three relatively unrelated portions of the memory, i.e., the isolated node, the ground, and the bit line, requires a relatively complex layout that significantly decreases the density of the memory. Thus, there remains the problem of how to design and fabricate an FeRAM that is as fast, failure resistant and dense as a conventional DRAM.
3. Solution to the Problem
The present invention provides a memory cell design that utilizes a shunt that significantly reduces the voltage across the memory element at times when the memory element is not being written to or read. By “shunt” is meant a simple switch or other direct electrical connection, such as a transistor or a diode. A “shunt” or a “shunt system” herein does not include a power source, such as a system supply voltage.
A ferroelectric memory element always includes a plurality of memory elements, and the shunt generally connects two different memory elements.
In a memory cell design that utilizes a plate line that is common to a plurality of different capacitors, a second shunt is connected between the TC node and the. common plate line.
In the preferred embodiment, adjacent TC nodes in the same row are shunted together, and there is only one shunt to the plate line every eight to thirty-two memory cells. This saves chip area.
In a memory cell design that utilizes a ferroelectric capacitor as the memory element, the shunt may connect the electrodes of the capacitor.
The shunt may be passive or active. Examples of a passive shunt include a Schottky diode, back-to-back diodes, and a resistor having a resistance sufficiently high to permit the desired coercive voltage to be applied during the read and write cycles and sufficiently low that current flows to the TC node from the plate line at least as fast as it leaks off the TC node due to leakage. An example of an active shunt is a transistor.
If the shunt is a transistor, and the plate line is raised to the full supply voltage, the shunt line connected to the shunt transistor gate is boosted. This ensures that the full supply voltage will pass through the shunt.
The shunt system is formed in the same process steps as the cell transistor and the cell capacitor. Thus, no additional-process steps are required to fabricate the shunt system.
The shunt system, for the most part, is located in areas of the chip that are redundant or contain other conventional cell parts, such as the bit line, at other levels in the layer structure. Thus, in general, the shunt system utilizes little additional chip area.
The
Celis Semiconductor Corporation
Duft, Graziano & Forest, P.C.
Nelms David
Tran M.
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