Ferroelectric memory with an intrinsic access transistor...

Details Ferroelectric memory with an intrinsic access transistor... Ferroelectric memory with an intrinsic access transistor...

2006-06-06

2006-06-06

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S190000, C365S189070, C365S202000

Reexamination Certificate

active

07057917

ABSTRACT:
A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

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D. Takashima et al., “A Sub-40ns Random-Access Chain FRAM Architecture with a 7ns Cell-Plate-Line Drive,” ISSCC Digest of Technical Papers, Feb. 15, 1999, pp. 102-103, and 450.

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