Ferroelectric memory integrated circuit with improved...

Details Ferroelectric memory integrated circuit with improved... Ferroelectric memory integrated circuit with improved...

2005-02-22

2005-02-22

Pham, Hoai (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S303000, C257S306000

Reexamination Certificate

active

06858890

ABSTRACT:
An IC with memory cells arranged in a chained architecture is disclosed. The top local interconnect between the top capacitor electrodes and active area is achieved by using a strap. The use of a strap eliminates the need for additional metal layer which reduces manufacturing costs. Furthermore, sidewall spacers are used to isolate the strap from the different layers of the capacitors. The use of spacers advantageously enables the strap to be self-aligned.

REFERENCES:
patent: 5330931 (1994-07-01), Emesh et al.
patent: 5384287 (1995-01-01), Fukase
patent: 5396095 (1995-03-01), Wolters et al.
patent: 6121649 (2000-09-01), Kunishima
patent: 6235573 (2001-05-01), Lee et al.
patent: 6242299 (2001-06-01), Hickert
patent: 6399974 (2002-06-01), Ohtsuki
patent: 0 877 422 (1998-11-01), None
Ozaki et al., A Fully Planalized 8M Bit Ferroeloetric RAM with “Chain” Cell Structure, 2001 Symposium on VLSI Technology Digest of Technical Papers, Jun. 12, 2001, p. 113-114.

Affiliated with

Also associated with

Rating

Ferroelectric memory integrated circuit with improved... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Ferroelectric memory integrated circuit with improved..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Ferroelectric memory integrated circuit with improved... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3463025