Ferroelectric memory element and method for manufacturing...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S751000

Reexamination Certificate

active

07459738

ABSTRACT:
A ferroelectric memory element has a memory cell array including memory cells arranged in a matrix configuration, each of the memory cells having a lower electrode, an upper electrode arranged in a direction intersecting the lower electrode, and a ferroelectric layer disposed at least in an intersecting area between the upper electrode and the lower electrode, wherein a hydrogen barrier film and a hydrogen barrier film are arranged at least below the memory cell array, and a bottom hydrogen barrier film is arranged below the memory cell array.

REFERENCES:
patent: 6066868 (2000-05-01), Evans, Jr.
patent: 6314283 (2001-11-01), Fielden
patent: 6635561 (2003-10-01), Kawai
patent: 6781184 (2004-08-01), Solayappan et al.
patent: 11-126881 (1999-05-01), None
patent: 2002-094000 (2002-03-01), None
patent: 2002-222933 (2002-08-01), None
patent: 2003-115545 (2003-04-01), None
patent: 2003-243625 (2003-08-01), None
patent: 2003-282825 (2003-10-01), None
patent: 2004-31553 (2004-01-01), None

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