Ferroelectric memory device with improved ferroelectric...

Details Ferroelectric memory device with improved ferroelectric... Ferroelectric memory device with improved ferroelectric...

1999-04-07

2001-08-28

Wojciechowicz, Edward (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S532000

Reexamination Certificate

active

06281536

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a ferroelectric memory device and a method of manufacturing the same. More particularly, the present invention relates to a ferroelectric memory device formed on a semiconductor substrate and composed of a memory cell transistor and a ferroelectric capacitance element for holding a stored data and a method of manufacturing the same.
2. Description of the Related Art
Recent years, the technology of a ferroelectric memory device is actively per developed which uses a ferroelectric film having a spontaneous polarization characteristic as a capacity insulating film. The ferroelectric memory device uses the polarization state of the ferroelectric capacitance element formed on a semiconductor substrate to store a data.
FIGS. 1
to
4
show an example of a unit memory cell of a ferroelectric memory device.
FIG. 1
is a plan view of the ferroelectric memory cell.
FIG. 2
shows a cross sectional view of the ferroelectric memory cell taken along the line a-a′ in
FIG. 1
, and
FIG. 3
shows a cross sectional view of the ferroelectric memory cell taken along the line b-b′ in FIG.
1
. Also,
FIG. 4
shows an equivalent circuit of the ferroelectric memory cell.
Referring to
FIG. 4
, a memory cell MC is composed of a field effect transistor Tr and a ferroelectric capacitance element Cf that is connected with one of a source and a drain of the transistor Tr. The other of the source and the drain of the transistor Tr is connected with a bit line BL. The gate electrode of the transistor Tr is connected with a word line WL. The other electrode of the ferroelectric capacitance element Cf is connected with a plate line PL. The memory cells MC structured in this way are arranged in a matrix so that a large-scaled nonvolatile ferroelectric memory device can be formed.
Next, an operation of the ferroelectric memory device will be described below.
The ferroelectric capacitance element Cf of the ferroelectric memory device shows a polarization characteristic, which depends on the history of applied voltage, as shown in FIG.
5
. In
FIG. 5
, a positive (+) direction of the applied voltage indicates that the voltage on the side of the plate line is higher than the voltage on the side of transistor Tr.
Now, in the ferroelectric memory cell shown in
FIG. 4
, a voltage of Vcc, e.g., 5 V is applied to the word line WL and the bit line BL, and 0 V is applied to the plate line PL. At that time, the ferroelectric capacitance; element Cf is set to the state shown in
FIG. 5
by a polarization state A. In this state, when only the voltage of the bit line BL is decreased to 0 V, the ferroelectric capacitance element Cf changes into the polarization state B shown in FIG.
5
. When this polarization state is made to correspond to “1”, it means that “1” is written in the memory cell MC. Also, when the voltage Vcc is applied to the word line WL and the plate line PL, and when 0 V is applied to the bit line BL, the ferroelectric capacitance element Cf changes into the polarization state C shown in FIG.
5
. When the voltage applied to the plate line PL is decreased from this state to 0 V, the ferroelectric capacitance element Cf changes into the polarization state D shown in FIG.
5
. For example, this means that “0” is written in the memory cell. It is preferable that the polarization state D in the application voltage of 0 V, i.e., the difference in a polarization value between the state D and state B (to be referred to as a residual polarization) is large. As a result, the reliability of data holding characteristic and rewriting weariness tolerance as the ferroelectric memory device can be achieved.
Next, the structure of this memory cell will be described.
FIG. 2
shows the cross sectional view of the memory cell taken along the line a-a′ of
FIG. 1
, and
FIG. 3
shows the cross sectional view of the memory cell taken along the dotted line b-b′ of FIG.
1
. As shown in
FIGS. 1
to
3
, the source/drain n
+
diffusion layers
8
are formed in surface regions of a p-type silicon substrate
1
. A gate electrode
7
is formed through a gate insulating film (not illustrated) on the p-type silicon substrate
1
. Thus, the field effect transistor as a memory cell transistor Tr is formed.
The bit line BL
6
mainly composed of Al is connected with one of the source and drain diffusion layers
8
of the field effect transistor Tr. A ferroelectric capacitance element Cf which is composed by a lower electrode
3
, a ferroelectric film
4
and an upper electrode
5
is formed on the field effect transistor Tr through an interlayer insulating film (SiO
2
). The upper electrode
5
is connected with one of the source and drain diffusion layers
8
of the field effect transistor Tr by a wiring layer
10
. In the conventional example, the word line WL
7
is used as the gate electrode of the field effect transistor Tr, and the plate line PL
3
is used as the lower electrode
3
of the ferroelectric capacitance element Cf. The ferroelectric film
4
is formed of a substance such as PZT (PbZr
x
Ti
1-x
O
3
) and SBT(SrBi
2
Ta
2
O
9
).
A ferroelectric film is generally formed in an oxidizing ambience. Also, an annealing process in an oxygen ambience often becomes necessary because of the stabilization of the ferroelectric film after the ferroelectric film is formed. For this reason, oxidization resistant noble metal such as Pt and Ir or a conductive oxide such as IrO
2
and RuO
2
are used as the lower electrode
3
and the upper electrode
5
. The wiring layers
6
and
10
are required to have the easiness of fine pattern formation, the excellent fitness to Si and SiO
2
, and a low resistivity. For example, a multi-layer film formed of Ti, TiN and Al is used as the wiring layer. Because Al has the fine pattern formability, corrosion resistance property, and a low resistivity, Al is widely used as the wiring layer material.
However, when Al and Si contact in the diffusion layer, Si atoms diffuse into the Al wiring layer in heat treatment to sometimes destroy the PN junction between the diffusion layer and the Si semiconductor substrate. For this reason, a TiN film is often used as a barrier film to prevent the mutual diffusion of the Al atoms and the Si atoms. Also, a Ti film is formed under the TiN film. Thus, for example, a laminate layer in which the Ti film, the TiN film and the Al film are laminated in this order from the bottom to form the multi-layer wiring layer. This is because the TiN film is inferior in the fitness with the Si film or the SiO
2
film so that a contact resistance with the Si film or the SiO
2
film is high.
Also, it is necessary to achieve a good electric connection between the Al film of the wiring layer
10
and a noble metal film, such as a Pt film which is used for the lower electrode
3
and the upper electrode
5
. Therefore, the technique in which a barrier layer which contains Ti as a main component is provided between the Al film and the Pt film is described in Japanese Laid Open Patent Application (JP-A-Heisei 6-120072).
Next, a manufacturing method of the ferroelectric memory cell of the conventional example shown in
FIG. 4
will be described with reference to the drawings.
FIGS. 6A
to
6
C show cross sectional views of the conventional memory cell in the manufacturing process of the conventional memory cell.
As shown in
FIG. 6A
, a ferroelectric capacitance element Cf is composed of a lower electrode
3
, a ferroelectric film
4
and an upper electrode
5
. The ferroelectric capacitance element Cf is formed on an interlayer insulating film which is formed on a silicon substrate
1
, in which a semiconductor integrated circuit such as memory cell transistors Tr is embedded. A protecting film is formed on the ferroelectric capacitance element Cf.
Next, as shown in
FIG. 6B
, contact holes
21
and
22
are formed to reach the upper electrode
5
of the capacitance element Cf and the diffusion layer
8
of the field effect transistor Tr.
Next, as shown in
FIG. 6C

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