Ferroelectric memory device with a high-speed read circuit

Details Ferroelectric memory device with a high-speed read circuit Ferroelectric memory device with a high-speed read circuit

1998-12-22

2001-08-21

Nelms, David (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S189090, C365S189040

Reexamination Certificate

active

06278630

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a ferroelectric memory device having a plurality of sets of bit lines, to which are connected a plurality of memory cells made up of one capacitor using a ferroelectric film and one MOS transistor, and differential sense amplifiers that can be connected to said bit lines. The ferroelectric memory device stores information by making the direction of polarization of the ferroelectric film correspond to binary information.
2. Description of the Related Art
In a ferroelectric memory device using a one-transistor one-capacitor type (lTlC type) memory cell, a reference voltage must be generated to determine whether data read from the memory cell is logic “0” or logic “1”. One type of device employs a dummy cell. One example of such a dummy cell construction is disclosed in Japanese Patent Laid-open No. 192476/95 and Japanese Patent Laid-open No. 93978/95. In this method, dummy cells are prepared in which logic “1” and “0” are respectively written to two ferroelectric capacitors, data are read from both dummy cells, and the reference potential is generated by averaging their values.
The method disclosed in Japanese Patent Laid-open No. 93978/95 will be described with reference to FIG.
1
. In the figure, logic “1” and “0” are written in dummy cells DMCa
1
and DMCa
2
, respectively. After precharging bit lines BLa
1
and BLa
2
, dummy cells DMCa
1
and DMCa
2
are selected by word lines DWLa
1
and DWLa
2
, and signal potentials corresponding to “1” and “0” are generated on bit lines BLa
1
and BLa
2
. Thereafter, transistor TSW
1
is rendered conductive by a bit line short-circuit signal to generate a voltage on the bit line corresponding to the midpoint between “1” and “0”. If a read from memory cell MCa
1
takes place after rendering transistor TSW
1
non-conductive and again precharging bit line BLa
1
, then bit line BLa
1
becomes a potential corresponding to “1” or “0” read from memory cell MCa
1
and bit line BLa
2
becomes a potential corresponding to the midpoint between “1” and “0”, thereby providing a one-transistor one-capacitor type ferroelectric memory device. Japanese Patent Laid-open No. 192476/95 discloses a construction in which the reference potential generated in a dummy cell is stored in an electronic memory unit to avoid subsequent generation of the reference potential. Thus, deterioration of the dummy cell due to film fatigue can be suppressed.
Other examples of dummy cell construction are disclosed in, for example, Japanese Patent Laid-open No. 301093/90 and U.S. Pat. No. 4,873,664 in which the size of the ferroelectric capacitor of dummy cells is made different from that of memory cells, in order to generate a reference potential.
The method disclosed in Japanese Patent Laid-open No. 301093/90 will be next described with reference to FIG.
2
. In the figure, a signal potential is generated on bit line BLal by selecting memory cell MCa
1
by means of word line WLa
1
and by driving plate line PLa
1
. Dummy cell DMCa
1
is selected by word line DWLa
1
, and a reference potential is generated on bit line BLa
2
by driving plate line DPLa
1
. The capacitor size in the dummy cell is made smaller than that of the memory cell, and moreover, the polarization direction is set such that polarization inversion always occurs when a reference potential is generated. In addition, CFa
1
is selected such that its capacitance when polarization is not inverted is smaller than the capacitance of DCFa
1
during polarization inversion. The capacitance of DCFa
1
is therefore smaller than the capacitance of CFa
1
during polarization inversion and greater than the capacitance when polarization is not inverted. A signal potential can thus be generated at BLa
2
that corresponds to the midpoint between logic “1” and “0”. Although the size of DCFa
1
is made smaller than that of CFa
1
in the above-described method, as disclosed in U.S. Pat. No. 4,873,664, the same effect can be obtained by both making DCFa
1
bigger than that of CFa
1
and by setting the direction of polarization such that polarization inversion never occurs when the reference potential is generated.
Another example of a dummy cell construction is described in Japanese Patent Laid-open No. 114741/93. In this example, a capacitor using a normal dielectric is employed as the capacitor of the dummy cell, and the accumulated charge of the dummy cell capacitor is used to boost the read-out signal potential such that the precharge potential is a potential corresponding to the midpoint between logic “1” and “0”.
This method will be described is detail with reference to FIG.
3
. In the figure, VCC/2 is supplied from the outside to one terminal of memory capacitor CFa
1
. Memory cell MCa
1
is selected by word line WLa
1
, and the signal potential is generated on bit line BLa
1
. Dummy cell capacitor DCa
1
is selected by dummy cell word line DWLa
1
, and boosts the potential of bit line BLa
1
. During a read operation, bit lines BLa
1
and Bla
2
are first precharged to VCC, following which word line WLa
1
is selected and data are read into the bit lines. Dummy cell word line DWLa
1
is then selected and the bit line potential is boosted. The capacitance used for the dummy cell at this time is such that the bit line potential when boosted is higher than the precharged potential when data is logic “1” and lower than the precharged potential when data is logic “0”. As a result, the precharge potential of BLa
2
is used as the reference potential, data can be sensed by sense amplifier SA.
In another method of generating a reference voltage, a reference voltage is generated in a memory cell without using a dummy cell. As an example, U.S. Pat. No. 5,086,412 discloses one such reference voltage self-generating system. According to this form, reads are carried out twice consecutively from the same memory cell, the charge read the second time being taken as the reference voltage. Explanation is presented using
FIG. 4
,
FIG. 5
, and FIG.
6
and citing the above-described U.S. Pat. No. 5,086,412. Memory cell MCa
1
is selected by word line WLa
1
after precharging bit line BLa
1
, and when plate line PLa
1
is strobed (returning to the initial state after the plate line is strobed), a charge &Dgr;Q
1
is read on bit line BLa
1
by the transition from state A by way of state B to reach state C of
FIG. 5
when the data is logic “1”. When the data is logic “0”, &Dgr;Q
0
=0 is read on bit line BLa
1
because the transition is from state C to state B and then back to state C. The read charge is held in a sample & hold circuit by making TG
1
“H”. A second read is then carried out with respect to the same cell. Because memory cell MCa
1
has been subjected to a destructive read, the second read charge is sure to be &Dgr;Q
0
, and the charge at the second read is therefore the reference. The charge read with TG
2
at “H” is held in the sample & hold circuit and data are subsequently sensed by differential sense amplifier with TG
3
as “H”. In addition, bias capacitor CBIAS is added to the reference-side bit line BLR of the differential sense amplifier to enable a correct reading operation even in a case in which &Dgr;Q
0
=0 for both the first and second read charges. The addition of this bias capacitor CBIAS has the effect of adding an offset between the two inputs of the differential sense amplifier by changing the impedance of the bit line, thereby enabling a 1-transistor 1-capacitor type ferroelectric memory device that does not require a dummy cell.
The hysteresis characteristic of the ferroelectric shown in
FIG. 22
deteriorates with increase in retention time or with ferroelectric film fatigue depending on the number of times the memory cell is accessed. In other words, the hysteresis loop of the ferroelectric film of a memory cell in which the hysteresis loop is repeatedly reversed decreases due to fatigue.
FIG. 23
shows the effect upon the read bit line v

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