Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2000-03-15
2001-05-08
Phan, Trong (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S149000
Reexamination Certificate
active
06229730
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a ferroelectric memory device employing ferroelectric capacitors, and more particularly, to a ferroelectric memory device where ROM data stored at a manufacturing process can be retained. Especially, the ferroelectric memory device according to the present invention is more suitable a non-volatile memory provided in a micro controller, for example.
2. Description of the Related Art
In recent years, a ferroelectric memory device employing ferroelectric capacitors has been proposed as a non-volatile memory. The ferroelectric memory device stores and reads data by employing its hysteresis characteristic and residual polarization action included in a ferroelectric film of the ferroelectric capacitor. By applying an electric field to the ferroelectric capacitor in one direction, the ferroelectric capacitor becomes a polarizing state in one direction. Alternatively, by applying an electric field to the ferroelectric capacitor in the other direction, the ferroelectric capacitor becomes a polarizing state in the reversed direction. Such the polarizing state may be retained as a residual polarization even after an electric field applied to the ferroelectric capacitor is extinct. Therefore, the ferroelectric memory device is used as a non-volatile memory where data can be retained, even if a power is OFF.
FIG. 9
is a circuitry diagram of a ferroelectric memory cell according to the prior art. The structure of a memory cell MC of
FIG. 9
is called a 2T2C structure, in which one pair of transistors Q
1
, Q
2
and one pair of ferroelectric capacitors C
1
, C
2
, connected to each of the transistors are included. Each of the transistors Q
1
, Q
2
has a gate connected to a word line WL, a source or drain electrode to which one of bit line pairs BL, /BL is respectively connected. Additionally, the ferroelectric capacitors C
1
, C
2
are connected to a plate line PL. A sense amplifier
10
is connected to a bit line pairs BL, /BL. Data is recorded by polarizing one capacitor pair C
1
, C
2
of the memory cell MC shown in
FIG. 9
, and the recorded data is read out in the later-explained method.
FIG. 10
shows a hysteresis curve of the ferroelectric film.
FIG. 10
shows an applied electric field or voltage on the abscissa axis and a polarization charge on the ordinate axis. In the hysteresis curve, the polarizing state of the ferroelectric film is changed from a point K, for example, and is returned to the point K through points L, M, N.
FIG. 11
illustrates a definition of a polarizing direction of the ferroelectric capacitor in this description. In
FIG. 11
, each polarizing states K, L, M, N shown in
FIG. 10
are shown. A hysteresis characteristic of the ferroelectric film will be now explained according to
FIGS. 10 and 11
.
As shown in
FIG. 11
, when applying a downward electric field Ek to the ferroelectric capacitors C
1
, C
2
by applying a voltage of 5V, for example, a downward polarization charge −qs of
FIG. 11
is generated on the capacitors C
1
, C
2
. When the voltage applied between the capacitors C
1
, C
2
are removed from this state K, after that, the state is moved to the state L and the polarization charge −qs remains on the capacitors C
1
, C
2
. On the other hand, when a voltage of 5V is applied for the ferroelectric capacitors C
1
, C
2
, in the upward direction of
FIG. 11
, the upward electric field Em is applied and the status becomes a polarizing state M of the polarization charge +qs. Even if the voltage application to the capacitor is removed from this state M, the polarizing status of polarization charge +qs can be retained on the capacitors as the state N.
Therefore, in this description, the state K or M where the electric field or voltage is applied to the capacitors is shown by a bold arrow line, and the state L or N of residual polarization where there is no potential difference in the capacitor and the electric field is not applied is shown by a broken arrow line. The direction of arrow indicates each polarizing direction.
FIG. 12
is a timing chart of writing and reading data to the memory cell having a 2T2C structure according to the prior art. In this timing chart, a word line WL, a plate line PL, a sense amplifier operation, a bit line pairs BL, /BL, each polarizing direction of capacitors C
1
, C
2
are shown.
FIG. 12
shows the time on the abscess axis.
Data writing and reading operation modes to the memory cell of
FIG. 9
will be explained in accompanying with
FIGS. 10 and 12
. At first, it is assumed that data written in the ferroelectric memory cell is indefinite at time Wt
0
of a write cycle. The bit line pairs BL, /BL are reset to an intermediate potential between levels H and L, and the word line WL and the plate line PL are set to L level. When the word line WL is driven to H level at time Wt
1
, the transistors Q
1
, Q
2
of the memory cell become conductive, and one capacitor pair C
1
, C
2
are respectively connected to the bit line pair BL, /BL. Then, at time Wt
2
, the sense amplifier
10
is activated according to the written data to set the bit lines BL and /BL respectively to H and L levels. As a result, the downward electric field is applied to the ferroelectric capacitor C
1
and the state becomes the state K, which is the downward polarizing state. Then, no electric field is applied to the other ferroelectric capacitor C
2
so that the polarizing direction is not changed.
When the plate line PL is driven to H level at time Wt
3
, the capacitor C
2
that is connected to the bit line /BL of L level is polarized in the other direction reversed to the capacitor C
1
. In other words, the capacitor C
2
becomes the state M, and the capacitor C
1
becomes the state L. After the plate line PL is returned to L level and the capacitor C
1
is polarized again, then, the word line WL is returned to L level and the cell transistors Q
1
, Q
2
are OFF at time Wt
5
. For the reason, the capacitor C becomes the downward polarizing state L, and the capacitor C
2
becomes the upward polarizing state N. The polarization states are remained and are retained, even when the power is OFF.
In the reading operation mode, the bit line pair BL, /BL are pre-charged to 0V at time Rt
0
. When the word line WL is driven to H level at time Rt
1
and the plate line PL is driven to H level, then, the state of the capacitor C
1
is moved from the state L to the state M and its polarization is reversed. On the other hand, the state of the capacitor C
2
is moved from the state N to the state M. As a result, the ferroelectric capacitor C
1
, of which polarization is reversed, emits more charge than that of the ferroelectric capacitor C
2
, of which polarization is not reversed, to each bit line, thus a predetermined potential difference is generated between the bit line pair BL, /BL.
At time Rt
2
,the plate line PL is set to L level. As a result, although the potential of the bit line pair BL, /BL is slightly pull down, the above-described potential difference can be retained. At time Rt
3
, the potential difference between the bit line pair BL and /BL can be detected and be amplified by activating the sense amplifier
10
. As a result, the data stored in the ferroelectric capacitor can be read out through each bit line.
Since both of the capacitors C
1
, C
2
are in the upward polarizing state at time Rt
1
, the stored data is broken. Therefore, the result of amplifying the sense amplifier
10
is given to the ferroelectric capacitors C
1
, C
2
and data is rewritten by driving the plate line PL to H and L level respectively at each time Rt
4
and Rt
5
. When the word line WL is set to L level at time Rt
6
, then, a residual polarizing state according to the stored data may be retained in the capacitors of the memory cell.
The above-described ferroelectric memory device is used by building in a micro controller and is used as a rewritable ROM, for example. There are some cases where a program, in which a procedure of activating the micro controller is wr
Armstrong Westerman Hattori McLeland & Naughton LLP
Fujitsu Limited
Phan Trong
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