Ferroelectric memory device having single bit line coupled...

Details Ferroelectric memory device having single bit line coupled... Ferroelectric memory device having single bit line coupled...

2000-05-12

2001-02-13

Phan, Trong (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S203000

Reexamination Certificate

active

06188601

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device; and, more particularly, to a ferroelectric memory device having a single bit line coupled to at least one memory cell.
DESCRIPTION OF THE PRIOR ART
Referring to
FIG. 1
, there is shown a circuit diagram showing a conventional ferroelectric memory device. As shown, the conventional ferroelectric memory device includes a precharge circuit
110
, an equalization circuit
120
, a sense amplifier
130
, a memory cell array
140
, a reference voltage transfer circuit
150
and a reference voltage generation circuit
160
. The conventional ferroelectric memory device includes a pair of complementary bit lines BL
1
N and BL
1
T and a pair of complementary bit lines BL
2
N and BL
2
T.
The precharge circuit
110
coupled to the complementary bit lines BL
1
N, BL
1
T, BL
2
N and BL
2
T precharges the complementary bit lines BL
1
N, BL
1
T, BL
2
N and BL
2
T to ground in response to a precharge signal PBL.
The equalization circuit
120
coupled to the complementary bit lines BL
1
N, BL
1
T, BL
2
N and BL
2
T equalizes the bit lines BL
1
N, BL
1
T, BL
2
N and BL
2
T to a half of a supply voltage Vcc, i.e., Vcc/2, in response to an equalization signal EBL.
The sense amplifier
130
is coupled to the complementary bit lines BL
1
N, BL
1
T, BL
2
N and BL
2
T. The sense amplifier
130
senses and amplifies a voltage difference between the complementary bit lines BL
1
N and BL
1
T or the complementary bit lines BL
2
N and BL
2
T in response to PMOS and NMOS enable signals SAP and SAN at a read operation.
The memory cell array
140
includes a plurality of memory cells, wherein one of the memory cells has an N-channel metal oxide semiconductor (NMOS) transistor and a ferroelectric capacitor. A drain terminal of the NMOS transistor contained in the one of the memory cells is coupled to the complementary bit line BL
1
N, BL
1
T, BL
2
N or BL
2
T. Further, a gate terminal of the NMOS transistor contained in the one of the memory cells is coupled to a word line WL
1
or WL
2
. The ferroelectric capacitor is coupled between a plate line PL
1
and a source terminal of the NMOS transistor contained in the one of the memory cells. The reference voltage generation circuit
160
coupled to the complementary bit lines BL
1
N, BL
1
T, BL
2
N and BL
2
T generates a reference voltage to send the reference voltage to the reference voltage transfer circuit
150
. The reference voltage generation circuit
160
includes two dummy cells DC
1
and DC
2
, wherein the dummy cells DC
1
and DC
2
include the NMOS transistor and the capacitor, respectively.
The drain terminal of the NMOS transistor contained in the dummy cell DC
1
or DC
2
is coupled to the complementary bit line RBL or RBLB. Further, the gate terminal of the NMOS transistor contained in the dummy cell DC
1
or DC
2
is coupled to a word line DWL. The ferroelectric capacitor contained in the dummy cell DC
1
or DC
2
is coupled between a line coupled to the half of the supply voltage Vcc, i.e., Vcc/2, and the source terminal of the NMOS transistor contained in the dummy cell DC
1
or DC
2
. The complementary bit lines RBL and RBLB are precharged to ground in response to a precharge signal PDL. The complementary bit lines RBL and RBLB are equalized in response to an equalization signal EDL. The complementary bit lines RBL and RBLB are pulled down in the response to a pull-down control signal PDC.
The reference voltage transfer circuit
150
couples the complementary bit line BL
1
N or BL
1
T to the complementary bit line RBL in response to transfer control signals DTGN and DTGT, thereby transferring the reference voltage from the reference voltage generation circuit
160
through the complementary bit line BL
1
N or BL
1
T. Further, the reference voltage transfer circuit
150
couples the complementary bit line BL
2
N or BL
2
T to the complementary bit line RBLB in response to transfer control signals DTGN and DTGT, thereby transferring the reference voltage from the reference voltage generation circuit
160
through the complementary bit line BL
2
N or BL
2
T.
In the conventional ferroelectric memory device, the number of operation times of the dummy cell DC
1
or DC
2
contained in the reference voltage generation circuit
160
is greater than that of the one of memory cells contained in the memory cell array
140
. Further, the ferroelectric capacitor contained in the dummy cell DC
1
or DC
2
is fatigued faster than that contained in the one of the memory cells. Where the ferroelectric capacitor contained in the dummy cell DC
1
or DC
2
is fatigued, the ferroelectric capacitor can not provide the reference voltage to a sense amplifier. Accordingly, the sense amplifier can not effectively sense and amplify a difference between the reference voltage from a complementary bit line and a voltage from another complementary bit line. Further, there is a problem that the conventional ferroelectric memory device increases its chip size by employing the complementary bit lines.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a ferroelectric memory device having a single bit line that can effectively sense and amplify a difference between a reference voltage and a voltage from the single bit line coupled to at least one memory cell.
It is, therefore, another object of the present invention to provide a ferroelectric memory device that can reduce its chip size by employing a single bit line coupled to at least one memory cell.
In accordance with an aspect of the present invention, there is provided a semiconductor memory device, comprising: a single bit line; at least one memory cell coupled to said single bit line for storing a first charge corresponding to predetermined data; a reference voltage generation means for generating a reference voltage as a first voltage; a charge pump means for generating a second charge substantially corresponding to the reference voltage; a combination means for combining the first charge with the second charge at a read operation, thereby generating a second voltage; and a sense amplifier coupled to said single bit line for sensing and amplifying a difference between the first voltage and the second voltage, to thereby read out the predetermined data.


REFERENCES:
patent: 6028783 (2000-02-01), Allen et al.

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