Ferroelectric memory device having folded bit line architecture

Details Ferroelectric memory device having folded bit line architecture Ferroelectric memory device having folded bit line architecture

1999-10-28

2000-11-21

Mai, Son

Static information storage and retrieval

Systems using particular element

Ferroelectric

365 63, 257295, 257300, G11C 1122, H01L 2976, H01L 27108

Patent

active

061512435

ABSTRACT:
A ferroelectric memory device includes a plurality of groups of active areas, each active area having two memory cells, and a plurality of pairs of conductive lines arranged in a parallel fashion, each conductive line having a word line and a plate line, wherein a pair of the word line and the plate line are isolated through an insulating layer, wherein each group of the active areas are coupled to each pair of the conductive lines, thereby having a folded bit line architecture without increasing a chip size.

REFERENCES:
patent: 5541872 (1996-07-01), Lowrey et al.
patent: 5767541 (1998-06-01), Hanagasaki
patent: 5852571 (1998-12-01), Kinney
patent: 5969380 (1999-10-01), Seyyedy
patent: 5990507 (1999-11-01), Mochizuki et al.
patent: 5990508 (1999-11-01), Shinohara
patent: 6015990 (2000-01-01), Hieda et al.

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