Ferroelectric memory device having cell groups containing...

Details Ferroelectric memory device having cell groups containing... Ferroelectric memory device having cell groups containing...

2000-06-27

2001-09-11

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S149000, C365S203000

Reexamination Certificate

active

06288931

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device; and, more particularly, to a ferroelectric memory device including a plurality of cell groups, each cell group having a transistor and a plurality of ferroelectric capacitors commonly coupled to the transistor.
DESCRIPTION OF THE PRIOR ART
A memory cell of a conventional ferroelectric random access memory (FeRAM) includes one transistor and one ferroelectric capacitor. It is well known that a ferroelectric capacitor shows a hysteresis characteristic between the charge and the voltage applied to the two terminals of the ferroelectric capacitor.
FIG. 1A
shows a symbol of a ferroelectric capacitor with the two terminals, and
FIG. 1B
shows a hysteresis characteristic of a ferroelectric capacitor.
A characteristic of a ferroelectric capacitor will be described with reference to
FIGS. 1A and 1B
. An amount of charge stored in the ferroelectric capacitor varies according to a polarization state S
1
or S
2
even if the voltage difference between the two terminals is zero. Thus, binary logic data can be stored in the ferroelectric capacitor even in the absence of power supply. The ferroelectric capacitor differs from the linear capacitor on that point. The polarization states are varied with the voltage applied to the two terminals of the ferroelectric capacitor, so that the amount of charge stored in the ferroelectric capacitor is varied.
As shown in
FIG. 1B
, the polarization state of the ferroelectric capacitor is changed from the state S
1
to a state S
3
by a large negative voltage applied thereto. And the polarization sate is changed from the state S
3
to the state S
2
when the voltage difference between the two thermals is zero. As described above, the amount of the charge is varied with the applied voltage, so that the ferroelectric capacitor can be used as a storage element of a non-volatile memory device.
FIG. 1C
is a waveform showing a potential change
10
of a bit line caused by the charge sharing between a ferroelectric capacitor Cf and a bit line parasitic capacitor Cb in case where a voltage is applied to a plate line PL.
In
FIG. 1C
, reference symbols V
1
and V
0
denote a potential of a bit line when data “1” and “0” are stored in the ferroelectric capacitor Cf, respectively.
FIG. 2
is a circuit diagram illustrating an array
100
of conventional FeRAM memory cells, each of the memory cells having a folded bit line architecture. For example, a memory cell
20
for storing 1 bit of conventional FeRAM includes one NMOS transistor N
21
and one ferroelectric capacitor C
21
. A gate of the NMOS transistor N
21
is coupled to a word line WLO, a drain of the NMOS transistor N
21
is coupled to a bit line Bit
0
and the other a source of the NMOS transistor N
21
is coupled to the ferroelectric capacitor C
21
. Two electrodes of the ferroelectric capacitor C
21
are coupled to the NMOS transistor N
21
and a cell plate line PL
0
, respectively.
First electrodes of each ferroelectric capacitor C
21
to C
28
are coupled to NMOS transistors N
21
to N
28
, respectively, and second electrodes of each ferroelectric capacitor C
21
to C
28
is commonly coupled to the plate line PL
0
. The word lines WL
0
to WL
3
are perpendicular to the bit lines Bit
0
to Bitb
3
and parallel to the plate lines PL
0
and PL
1
.
A predetermined voltage must be applied to the two electrodes of the ferroelectric capacitors during a reading or a writing operation. Therefore, a high state voltage Vcc or a low state voltage Vss is applied to the plate line PL
0
.
The read operation of the conventional FeRAM device will be described in detail with reference to
FIGS. 1B and 2
.
In order to read data stored in the ferroelectric capacitor C
21
, the word line WL
0
is selected and activated, and the rest word lines WL
1
, WL
2
and WL
3
are remained as inactivated. A high level signal is applied to the plate line PLS
0
coupled to the gate of an NMOS transistor N
20
. A low signal is applied to the global plate line GPL coupled to the NMOS transistor N
20
through an inverter INV
20
. As a result, the high level signal is applied to the plate line PL
0
.
As described above, the bit line BitO and the storage node S
1
are precharged to the ground level, so that the voltage between the two terminals of the ferroelectric capacitor C
21
becomes −Vcc.
Referring to
FIG. 1B
, the polarization state of ferroelectric capacitor is changed from state S
1
or S
2
to the direction of S
3
, when a negative voltage is applied to the ferroelectric capacitor C
21
. Therefore, the voltage of the bit line Bit
0
is changed according to the variation of the charge amount &Dgr;Q
1
or &Dgr;Q
1
.
As a result, the capacitance of the parasitic bit line capacitor Cb is changed. That is, data is transferred between the parasitic bit line capacitor Cb and the ferroelectric capacitor C
21
by a charge sharing.
In
FIG. 1B
, S
1
and S
2
denote logic data “1” and “0”, respectively. The polarization state S
1
is changed to the state corresponding to the voltage V
1
, and the polarization state S
2
is changed to a state corresponding to the voltage V
0
, when a large negative voltage is applied to the ferroelectric capacitor C
21
. The capacitance obtained by the change of the polarization state S
1
to the direction of the polarization state S
3
is larger than the capacitance obtained by the change the polarization state S
2
to the direction of the polarization state S
3
. Therefore, the voltage V
1
is lager than the voltage V
0
. This relation is expressed by the following equation:
Δ
⁢
 
⁢
V1
=
Cf1
Cf1
+
Cb
×
Δ
⁢
 
⁢
Vp
,
Δ
⁢
 
⁢
V0
=
Cf0
Cf0
+
Cb
×
Δ
⁢
 
⁢
Vp
(
Eq
.
 
⁢
1
)
where, &Dgr;Vp represents the amount of voltage variation of plate line, and
Cf1 and Cf0 represents the equivalent capacitance of data logic “1” and “0” states, respectively.
In Eq. 1, the &Dgr;V1 is larger than the &Dgr;V0 since the Cf1 is larger than the Cf0.
As described above, the memory cell of the conventional FeRAM includes one switching NMOS transistor and one ferroelectric capacitor. In order to drive a memory cell, a plurality of bit lines, word lines and plate lines coupled to each memory cell are driven, respectively. Therefore, the conventional FeRAM has the limitation in the improvement of the device integration.
SUMMARY OF THE INVENTION
It is an object of the present invention is to provide a ferroelectric memory device capable of increasing the integrity of device by coupling at least two memory cells to one bit line and one word line through one transistor.
In accordance with one aspect of the present invention, there is provided a ferroelectric memory device comprising: a plurality of cell groups, wherein each cell group includes a transistor and at least two ferroelectric capacitors commonly coupled to the transistor; at least one word line for selecting the cell groups; at least two plate lines for driving the capacitors contained in a memory cell of a selected cell group; and at least one bit line for transmitting data to the selected memory cell.
In accordance with another aspect of the present, there is provided a ferroelectric memory device comprising: a plurality of memory cells, wherein each memory cell includes a ferroelectric capacitor for storing data; a reference voltage generating means for generating a reference voltage; a sense amplifying means for sensing and amplifying signals outputted from the memory cell; a precharging means; a plurality of bit line pairs precharged by the precharging means, wherein each bit line pair includes a first bit line for transmitting data from the memory cell to the sense amplifying means and the second bit line for transmitting the reference voltage to the sense amplifying means; a plurality of cell groups, wherein each cell group includes a plurality of memory cells which are commonly coupled to the same word line and the same bit line pair through one transistor; and a plurality of plate li

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