Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-11-22
2002-12-17
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S295000, C257S300000, C257S306000
Reexamination Certificate
active
06495879
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a ferroelectric memory device having a protective layer and, more particularly, to a ferroelectric memory device having a ferroelectric capacitor and a memory cell transistor in combination in each memory cell.
(b) Description of a Related Art
A ferroelectric memory device including a ferroelectric capacitor having a ferroelectric film as a capacitor film is extensively developed for use in a variety of electronic applications. The ferroelectric capacitor stores data by using the state of polarization of the ferroelectric film sandwiched between electrodes of the ferroelectric capacitor, wherein the ferroelectric film has a remnant polarization capable of being switched in the direction thereof by an applied voltage.
FIG. 1
shows an example of a memory cell having a ferroelectric capacitor in a conventional ferroelectric memory device, and
FIG. 2
shows an equivalent circuit diagram of the memory cell of FIG.
1
. The memory cell
30
includes a cell transistor
24
implemented by a FET and a cell capacitor
25
implemented as a ferroelectric capacitor. The FET
24
has a pair of source/drain regions
18
including one connected to a bit line BL extending in a row direction and the other connected to a first electrode of the ferroelectric capacitor
25
, and a gate connected to a word line WL extending in a column direction. The ferroelectric capacitor
25
has a second electrode connected to a plate line PL extending in the column direction. A plurality of memory cells are arranged in a matrix to form a memory cell array of a large-scale ferroelectric memory device.
FIG. 3
shows a hysteresis polarization characteristic of the ferroelectric film, with the applied voltage (volts) and the polarization (&mgr;coulomb per centimeter) of the ferroelectric film being plotted on the abscissa and the ordinate, respectively. The applied voltage is plotted in a positive direction if the plate line PL is applied with a positive voltage with respect to the bit line BL. When the word line WL and the bit line BL are applied with 5 volts, for example, and the plate line PL is applied with zero volt, the ferroelectric film stays at point “A” of the polarization curve in
FIG. 3
, and then shits to point “B” if the bit line BL is subsequently applied with zero volt with the remaining lines being maintained at the previous voltages.
On the other hand, when the word line WL and the plate line PL are applied with 5 volts, with the bit line being applied with zero volt, the ferroelectric film stays at point “C”, and then shits to point “D” if the plate line PL is applied subsequently with zero volt. By defining “1” for the state of the ferroelectric film at point “B”, and “0” for the state at point “D”, the ferroelectric capacitor stores data after applying the described voltages.
It is desirable that the ferroelectric film have a large difference between the remnant polarizations at points “D” and “B” for improving the storage characteristic and programming. characteristic. The term “storage characteristic” means reliability of the ferroelectric capacitor storing the data without an error whereas the term “programming characteristics” means resistance or tolerance of the ferroelectric capacitor against defects due to a large number of times for overwriting of the stored data.
FIGS. 4 and 5
depict cross-sections of the memory cell of
FIG. 1
taken along lines IV—IV and V—V, respectively, in FIG.
1
. The cell transistor includes source/drain regions
18
implemented by n
+
-diffused regions in the surface region of the semiconductor substrate
11
, and a gate
17
formed on the semiconductor substrate
11
with an intervention of a gate oxide film not shown in the figure. The bit line including Al as a main component thereof is connected to one of the source/drain regions
18
of the cell transistor.
The ferroelectric capacitor
25
is disposed above the cell transistor, and includes a bottom electrode
13
, a ferroelectric film
14
and a top electrode
15
. The ferroelectric capacitor
25
is protected by a cover film
19
made of SiO
2
, for example.
An alumina (Al
2
O
3
) film may be interposed between the ferroelectric capacitor
25
and the cover film
19
for prevention of thermal evaporation of elements constituting the ferroelectric material during the fabrication process, as described in “Proceedings of International Symposium on Integrated Ferroelectrics”, for example. The top electrode
15
is connected to the other of the source/drain regions
18
through an interconnect layer
16
.
In the Configuration of the conventional ferroelectric memory device, the word line WL implements the gate electrodes
17
of the cell transistors, whereas the plate line PL implements the bottom electrodes
13
of the ferroelectric capacitors
25
. The ferroelectric film
14
is made from PZT [(Pb,La)(Zr,Ti)O
3
] or SBT [SrBi
2
(Nb,Ta)
2
O
9]
The ferroelectric film
14
is generally formed in an oxidation ambient, often followed by a thermal annealing treatment in an oxygen ambient for stabilization of the ferroelectric film
14
. In view of the thermal annealing, noble metals such as Pt or Ir, or conductive oxides such as IrO
2
and RuO
2
having an acid resistance are generally used for the material of the top and bottom electrodes. On the other hand, a layered structure including WSi
2
film, TiN film and Al film is generally used for the material of the interconnect layer
16
in view of the feasibility of fine patterning, excellent adherence with respect to Si or SiO
2
and a low resistivity.
In a thermal treatment during fabrication of the ferroelectric memory device, it is known that Si diffuses into the Al film if the Al film is disposed in direct contact with Si in the diffused region. This may cause destruction of the p-n junction formed between the diffused region
18
and the semiconductor substrate
11
. A TiN film is often used as a barrier film for prevention of the mutual diffusion between Al and Si, whereby the layered structure for the interconnect layer
16
includes, as mentioned above, WSi
2
, TiN and Al as viewed from the bottom. In this configuration, it is considered that TiN has a poor adherence with respect to Si and SiO
2
and a high contact resistance with respect to Si, and that WSi
2
has a function for suppressing degradation of the polarization characteristic of the ferroelectric material after formation of the interconnect layers, as described in Patent Publication JP-A-10-095846.
An interlayer dielectric film
20
such as silicon oxide film is deposited on the interconnect layer
16
, followed by formation of a protective layer (insulator film)
21
such as SiN
x
film or SiO
x
N
y
film for prevention of water, as described in Patent Publication JP-A-4-15957. The SiN
x
film or SiO
x
N
y
film as used herein protects the interconnect layer having Al as a main component thereof against corrosion due to water entering from atmosphere.
FIGS. 6A
to
6
C show sectional views, taken along line V—V in
FIG. 1
, of the memory cell in consecutive steps of fabrication thereof. In
FIG. 6A
, the ferroelectric capacitor
25
including the bottom electrode
13
, the ferroelectric film
14
and the top electrode
15
is formed on an interlayer dielectric film
26
, followed by formation of the cover film
19
thereon. Subsequently, via holes
27
are formed for exposing the diffused regions
18
of the substrate
11
and the top electrode
15
of the ferroelectric capacitor
25
, as shown in FIG.
6
B. Thereafter, the interconnect layer
16
for connecting one of the diffused regions
18
and the top electrode
15
as well as the bit line are formed. Further, the interlayer dielectric film
20
and the protective film
22
such as SiN
x
film or SiO
x
N
y
film are consecutively formed on the interconnect layer
16
and the bit line, as shown in FIG.
6
C. The protective film
22
is formed by using a plasma-enhanced CVD (PECVD) process at a substrate temperature of a
Chaudhuri Olik
Choate Hall & Stewart
Doan Theresa T.
NEC Corporation
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