Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2002-12-30
2004-02-10
Elms, Richard (Department: 2824)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S185070, C365S185090, C365S185230, C365S185260, C365S189070, C365S189090, C365S230060
Reexamination Certificate
active
06690600
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to ferroelectric memory devices, and more specifically, to a ferroelectric memory device which comprises a reference generator for regulating the level of reference voltage by using a programmable register, which programs the level of output signal by externally applied signals and maintains the program result without power, to control the on/off of switches regulating the capacitance of capacitors connected to driving power and a redundant decoder using the programmable register as on/off controller of a switch for programming redundant address program.
2. Description of the Background Art
Generally, a ferroelectric random access memory (hereinafter, referred to as ‘FRAM’) has attracted considerable attention as next generation memory device because it has a data processing speed as fast as a DRAM and conserves data even after the power is turned off.
The FRAM includes capacitors similar to the DRAM, but the capacitors have a ferroelectric substance for utilizing the characteristic of a high residual polarization of the ferroelectric substance in which data is not low even after eliminating an electric field applied thereto.
FIG. 1
is a characteristic curve illustrating a hysteresis loop of a general ferroelectric substance. As shown in
FIG. 1
, a polarization induced by an electric field does not vanish but keeps some strength (‘d’ or ‘a’ state) even after the electric field is cleared due to existence of a residual (or spontaneous) polarization. These ‘d’ and ‘a’ states may be assigned to binary values of ‘1’ and ‘0’ for use as a memory cell.
FIG. 2
is a structural diagram illustrating a unit cell of the FRAM device. As shown in
FIG. 2
, the unit cell of the conventional FRAM is provided with a bitline B/L arranged in one direction and a wordline W/L arranged in another direction vertical to the bitline B/L. A plateline P/L is arranged parallel to the wordline and spaced at a predetermined interval. The unit cell is also provided with a transistor Ti having a gate connected to an adjacent wordline W/L and a source connected to an adjacent bitline B/L, and a ferroelectric capacitor FC
1
having the first terminal of the two terminals connected to the drain terminal of the transistor T
1
and the second terminal of the two terminals connected to the plateline P/L.
The data input/output operation of the conventional FRAM is now described as follows.
FIG. 3
a
is a timing diagram illustrating a write mode of the FRAM while
FIG. 3
b
is a timing diagram illustrating a read mode of the FRAM.
Referring to
FIG. 3
a
, when a chip enable signal CSBpad applied externally transits from a high to low level and simultaneously a write enable signal WEBpad also transits from a high to low level, the array is enabled to start a write mode. Thereafter, when ah address is decoded in a write mode, a pulse applied to a corresponding wordline transits from a “low” to “high” level, thereby selecting the cell.
In order to write a binary logic value “1” in the selected cell, a “high” signal is applied to a bitline while a “low” signal is applied to a plateline P/L. In order to write a binary logic value “0” in the cell, a “low” signal is applied to a bitline while a “high” signal is applied to a plateline P/L.
Referring to
FIG. 3
b
, when a chip enable signal CSBpad externally transits from a “high” to “low” level, all bitlines are equalized to a “low” level by an equalization signal before selection of a required wordline.
After each bitline is deactivated, an address is decoded to transit a signal on the required wordline from a “low” to “high” level, thereby selecting a corresponding unit cell. A “high” signal is applied to a plateline of the selected cell to cancel a data Qs corresponding to the logic value “1” stored in the FRAM. If the logic value “0” is stored in the FRAM, a corresponding data Qns will not be destroyed.
The destroyed and non-destroyed data output different values, respectively, according to the above-described hysteresis loop characteristics. As a result, a sense amplifier senses logic values “1” or “0”. In other words, as shown in the hysteresis loop of
FIG. 1
, the state moves from ‘d’to ‘f’when the data is destroyed while the state moves from ‘a’to ‘f’when the data is not destroyed.
As a result, the destroyed data amplified by the enabled sense amplifier outputs a logic value “1” while the non-destroyed data amplified by the sense amplifier outputs a logic value “0”. After the sense amplifier amplifies the data, the data should be recovered into the original data. Accordingly, when a high' signal is applied to the required wordline, the plateline is disabled from “high” to “low”.
There are problems in the conventional FRAM as follows. In a conventional reference voltage generating means, levels of output voltages are fixed when they are produced. In a redundancy processing method using conventional metal/polysilicon lines, or fuses may not be recovered because they are physically removed by using a laser cutting.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a reference generator for regulating a reference voltage by using a programmable register which can program its output signal with externally applied signals and maintain the program result without power to control on/off of switches regulating capacitance of capacitors connected to driving source.
It is another object of the present invention to provide a ferroelectric memory device which may easily recover an error by introducing a switch and a programmable register which controls the on/off of the switch into a redundant address decoder.
In order to achieve the above-described objects, there is provided a ferroelectric memory device, comprising: a reference programming means for regulating and outputting a reference level control signal whose voltage level can be programmed with the programmable register; and a reference voltage generating means for outputting a reference voltage according to the reference level control signal.
There is also provided a method of programming the ferroelectric memory device of the present invention, comprising the steps of: decoding signals inputted to a signal input unit; activating a program mode operating signal corresponding to a program mode and deactivating the signal input unit; and performing the program mode in response to the program mode operating signal.
REFERENCES:
patent: 5995406 (1999-11-01), Kraus et al.
patent: 6381172 (2002-04-01), Banks
Elms Richard
Hynix / Semiconductor Inc.
Luu Pho M.
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