Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2000-06-19
2001-03-06
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S149000
Reexamination Certificate
active
06198654
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a ferroelectric memory device, and more particularly to a device structure of a non-volatile memory using a ferroelectric thin film and a method of reading data from this ferroelectric memory device.
2. Description of Related Art
One example of ferroelectric memory devices which have been proposed is one having a cell structure comprised of transistors and a stored capacitance element (capacitor). This stored capacitance element is called a “ferroelectric capacitor” since ferroelectric film is used. As such a ferroelectric memory cell, the 1T1C type, where one memory cell is comprised of one transistor and one ferroelectric capacitor, and the 2T2C type, where one memory cell is comprised of two transistors and two ferroelectric capacitors are known.
Now, the operation principle of the 1T1C type ferroelectric memory device will be briefly described with reference to FIG.
12
.
FIG. 12
is a circuit diagram of a conventional 1T1C memory device.
One memory cell
100
, which is comprised of one transistor
102
and one ferroelectric capacitor
104
, is positioned at the intersection between the word line (WL) and the bit line (BL). One electrode of the ferroelectric capacitor
104
is connected to BL via the transistor
102
which turns the connection with BL ON and OFF, that is, via the main current path of this transistor
102
. The other electrode of the ferroelectric capacitor is connected to a plate line (PL). BL is also connected to a sense amplifier
106
.
The stored information is stored to be one of the two states of the ferroelectric capacitor
104
with respect to the applied voltage 0V. For example, in the above mentioned ferroelectric memory device, if one memory cell
100
is selected by WL, BL is set to the ground potential (0V), and a positive voltage is applied to PL, then the polarization direction of the ferroelectric capacitor
104
becomes a first direction. This state is stored as information “0”. If the memory cell
100
is selected, a positive voltage is applied to BL, and PL is set to 0, then the polarization direction of the ferroelectric capacitor
104
becomes a second direction, which is the opposite direction of the first direction. This state is stored as information “1”.
A method of reading data in such an 1T1C memory cell will now be described.
For the data reading operation, BL of the target memory cell
100
is pre-charged to the ground potential (0V) first, then a positive voltage is applied to PL. If the ferroelectric capacitor
104
is polarized in the second direction, that is the (←) direction, the polarization direction of the ferroelectric capacitor
104
is inverted by this reading operation. If the ferroelectric capacitor
104
is polarized in the first direction, that is the (→) direction, on the other hand, polarization inversion is not caused by this reading operation. During these reading operations, the potential of BL changes according to the polarization state of the ferroelectric capacitor
104
when the data was written. This potential is output as a different potential V
1
or V
0
by the sense amplifier
106
. For example, the potential of V
1
is higher than V
0
.
To determine these signals by the sense amplifier
106
, the reference potential (also called “reference signal”) V
ref
must be input to the sense amplifier
106
.
If the reference potential V
ref
is an intermediate potential of V
1
and V
0
, and if the potential of BL is higher than V
ref
in the sense amplifier
106
, this means that V
1
, that is, the stored information of the ferroelectric capacitor
104
, is “1”. If the potential of BL is lower than V
ref
, this means that V
0
, that is, the stored information, is “0”.
A dummy cell method is normally used to generate such reference potential V
ref
. In the case of the configuration in
FIG. 12
, a memory cell
108
having a similar structure as the memory cell
100
is disposed as a dummy cell. This dummy cell
108
has one transistor
110
and one ferroelectric capacitor
112
. The dummy cell
108
is disposed at the intersection between a bit complementary line (/BL) connected to the sense amplifier
106
and a word line for dummy cell (D-WL). One electrode of the ferroelectric capacitor
112
is connected to /BL via a transistor
110
which turns the connection with /BL ON and OFF, that is, via the main current path of this transistor
110
. The other electrode of the ferroelectric capacitor
112
is connected to a plate line for dummy cell (D-PL) . It is necessary, however, that the stored capacitance of the ferroelectric capacitor
112
of the dummy cell
108
be set to a capacitance which is different from the ferroelectric capacitor
102
of the original memory cell
100
, so that the reference potential (V
ref
) generated in /BL becomes a voltage value (set value) between V
1
and V
0
.
The dummy cell
108
, however, is always used to read data from the ferroelectric memory device no matter which memory cell is selected. Therefore, the ferroelectric film constituting the ferroelectric capacitor
112
of the dummy cell
108
tends to have “fatigue phenomena”, such as where the polarization quantity changes while repeating polarization inversion (fatigue) or where the hysteresis characteristic shifts by a unipolar pulse (imprinting) These fatigue phenomena may cause the reference potential from the dummy cell to deviate from the above mentioned set value. Because of this, a conventional ferroelectric memory device has the problem where the possibility of reading errors is high.
When a 2T2C type memory cell is used, the memory cell is comprised of an original memory cell and a complementary memory cell for writing data so that a complementary signal of the signal from the original memory cell is input to the sense amplifier.
When the data is read, the signal from the original memory cell and the complementary signal from the complementary memory cell are input to the sense amplifier, so the reading margin is about two times that of an 1T1C type memory cell. Therefore, in the case of this type of ferroelectric memory device, the possibility of reading errors decreases. Also, the ferroelectric films of two capacitors (original cell and complementary cell) in one memory cell deteriorate at an equal rate, since the same number of times of writing is executed. Therefore, in the case of a 2T2C type memory device, operation is more stable than a 1T1C type memory device where deterioration of ferroelectric film of a dummy cell is more conspicuous.
However, in the case of 2T2C, a high integration of a ferroelectric memory device is impossible since the size of a memory cell is larger than that of the 1T1C type. Therefore, in terms of shrinking cell size, the 1T1C type is preferable.
SUMMARY OF THE INVENTION
With the foregoing in view, the first object of the present invention is to provide a ferroelectric memory device which cell size is smaller than the 2T2C type so that high integration is possible.
The second object of the present invention is to provide a method of reading data from such a ferroelectric memory device without any reading errors.
To achieve the above first object, a ferroelectric memory device of the present invention has the following unique configuration. That is, the ferroelectric memory device of the present invention comprises at least one memory cell, a word line, a first bit line, a second bit line, a capacitor, a sub-bit line and a sense amplifier. According to the present invention, the memory cell further comprises one ferroelectric capacitor and a first transistor where one end of a main current path is connected to one electrode of the ferroelectric capacitor. Also, according to the present invention, the word line is connected to a control electrode of the first transistor. Also, according to the present invention, the first bit line is connected to the other end of the main current path of the first transistor. Also, according to the present invention, the second bit line is connect
Burdett James R.
Frank Robert
Hoang Huan
Oki Electric Industry Co. Ltd.
Venable
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