Ferroelectric memory device and method for reading data from...

Static information storage and retrieval – Systems using particular element – Ferroelectric

Reexamination Certificate

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C365S189070

Reexamination Certificate

active

06912149

ABSTRACT:
A ferroelectric memory device includes a plurality of bit line pairs, a plurality of sense amplifiers, a plurality of memory cells, a plurality of reference cells, and a control circuit. Each of the bit line pairs is composed of first and second bit lines. Each of the sense amplifiers amplifies a potential difference across the corresponding bit line pair. The memory cells are provided for the respective bit line pairs and each composed of a transistor and a ferroelectric capacitor. The reference cells are provided for the respective bit line pairs and each composed of a transistor and a ferroelectric capacitor. In addition, each of the reference cells on each of the bit line pairs retains data different from data of a reference cell on the adjacent bit line pair. The control circuit drives the sense amplifiers, the memory cells, and the reference cells. During the drive of the sense amplifier, the control circuit inactivates a reference word line connected to the reference cell.

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patent: WO 97/36300 (1997-10-01), None
Yeonbae chung et al., “A 3.3-V 4-Mb Nonvolatile Ferroelectric RAM with Selectively-Driven Double-Pulsed Plate Read/Write-Back Scheme,” Symposium on VLSI Circuits Digest of Technical Papers, pp. 97-97, 1999.

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