Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
1998-12-30
2001-03-27
Nelms, David (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S203000, C365S227000, C365S230060
Reexamination Certificate
active
06208550
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a ferroelectric memory device using ferroelectric storage cells; and, more particularly, to such a memory device without using separate reference cell for producing a reference voltage which has been used in sensing the data level of the storage cell.
A ferroelectric non-volatile memory device uses a storage capacitor consisting of ferroelectric material sandwiched between two metal electrodes.
FIG. 1
shows a hysteresis loop of the charge variation with respect to the voltage applied to the two electrodes A and B of the capacitor represented as a symbol in FIG.
1
. Because the ferroelectric capacitor has two stable charge states P1 and P2 when applied voltage is 0 V, binary data can be stored even when power is not supplied. These two stable states can be considered a bistable capacitor which can be used as a storage element of a non-volatile memory device. In the ferroelectric capacitor, the polarization state (alignment in parallel) within the ferroelectric material is varied depending on the value of the applied voltage, which causes the variation of the stored charges. For example, when the ferroelectric capacitor maintains the polarization state of P1 of FIG.
1
and sufficiently large negative voltage, e.g., −3 V or less is applied to the capacitor, the capacitor switches to the polarization state of P3 along the hysteresis loop. If the negative voltage is then removed from the capacitor so as to make the voltage to be 0 V, the capacitor changes to the P2 state. The charge state of the ferroelectric capacitor changes along the arrow direction depending on the applied voltage, so that digital information can be obtained by detecting the variation of the charge induced in the capacitor in the function of the applied voltage.
During the read operation of the ferroelectric memory device, when a word line is selected, a positive bit line (BL) exhibits a different voltage V0 or V1 which is determined by the stored data in the memory cell (“0” or “1”) . The voltage signals V0 and V1 are small signals, which need to be amplified by using e.g., a sense amplifier. For sensing and amplifying the voltage signals V0 and V1, a reference signal Vref must be applied to a negative bit line (/BL). The sense amplifier detects whether the voltage of the BL is greater or smaller than the reference voltage Vref applied to the /BL, and amplifies the voltage difference to read out the data “0” or “1” stored in the storage cell.
Accordingly, the value of Vref must be between V0 and V1, and if the voltage difference between V0 and V1 becomes greater, more accurate data read operation is possible. Further, if the capacitance of the main storage cell becomes larger, the voltage difference of V1 and V0 can be made greater. However, this inevitably causes the increase of the cell size.
2. Description of the Related Art
For applying to the /BL the Vref in the middle of V0 and V1, numerous reference cells have been developed in the prior art as described in e.g., “1994, Int. Solid State Circuit Conf., paper FA16.2”, “1996, Int. Solid State Circuit Conf., paper SP23.1”, and “1996, Symp., VLSI Circuit, paper 5.2”.
However, above reference cells are not sufficient to produce reliable middle value between the V0 and the V1. Moreover, the reference cell itself consumes chip area, may cause a noise, and makes the chip operation complicated.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a memory device without using separate reference cell for producing a reference voltage which has been used in sensing the data level of the storage cell.
In accordance with one aspect of the present invention, there is provided a ferroelectric memory device provided with memory arrays which are comprised a plurality of word line and a plurality of positive and negative bit lines which are crossed over each other in a matrix form, and sense amplifiers to detect and amplify voltage difference between the positive and the negative bit lines, and the memory device comprises: voltage generating means for producing positively pumped supply voltage; precharge voltage selecting means, responsive to least significant bits of row addresses from a word line driving circuit, for selecting the positively pumped supply voltage as a precharge voltage for the positive bit line and a normal supply voltage as a precharge voltage for the negative bit line; and precharging means for precharging the positive and the negative bit lines respectively to the positively pumped supply voltage and the normal supply voltage from the precharge voltage selecting means.
In accordance with another aspect of the present invention, there is provided a method for operating a ferroelectric memory device provided with memory cells, each having a switching transistor and a ferroelectric capacitor for storing electric charges, and a plurality of positive and negative bit lines for transferring the electric charges, comprising the steps of: raising the positive bit line to a first positive voltage level and the negative bit line to a second positive voltage level lower than the first positive voltage level; turning on the switching transistor to induce a charge sharing effect between electric charges in both the ferroelectric capacitor and the positive bit line, so that a voltage difference is produced between the positive and the negative bit lines; and sensing the voltage difference and amplifying the voltage developed on the positive bit line to the second positive voltage level or to a ground voltage level depending on the electric charge stored in the ferroelectric capacitor.
Therefore, in accordance with the present invention, the precharge voltage of the positive bit line is increased so that the voltage difference between the positive and the negative bit lines is also increased regardless of the capacitor status. Hence a sensing margin of sense amplifiers and the reliability of the memory device can be improved. In addition, the memory device of the present invention does not use any separate reference cells but uses the voltage level of the negative bit line as a reference voltage for sensing the voltage difference between the positive and the negative bit lines. This results in reduction of the chip size and lower cost.
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Hyundai Electronics Industries Co,. Ltd.
Jacobson Price Holman & Stern PLLC
Le Thong
Nelms David
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