Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2001-05-02
2003-07-01
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S149000, C365S230060
Reexamination Certificate
active
06587366
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor memory device, and particularly to a ferroelectric memory device and operation method therefor.
2. Description of Related Art
Conventionally, in semiconductor memory devices, there is well known the so-called DRAM (dynamic memory) wherein electrical charges are stored in capacitors formed internally therein, and wherein data are stored according to the presence or absence of such charges. In recent years, devices wherein ferroelectric films are used as insulative films in such capacitors are being given much attention with respect to their high level of integration, high speed, and low power consumption.
One example of a ferroelectric memory device is disclosed in Reference 1 (T. Sumi et al.: “A 256 kb Nonvolatile Ferroelectric Memory at 3 V and 100 ns,” ISSCC Digest of Technical Papers, P 268-269 (February, 1994).”
FIG. 11
schematically shows the configuration of the ferroelectric memory device described in Reference 1.
In
FIG. 11
, one memory cell
508
is representatively diagrammed. In actual practice, however, this kind of memory cell is arranged in a matrix array to form a memory cell array
520
.
In the device shown in
FIG. 11
, a 2T2C type memory cell
508
is configured by two ferroelectric capacitors
500
and
502
and two MOSFETs
504
and
506
. The ferroelectric capacitor
500
is connected in series with the MOSFET
504
. Similarly, the ferroelectric capacitor
502
is connected in series with the MOSFET
506
. The terminals of the ferroelectric capacitors
500
and
502
the are not connected to the MOSFETs
504
and
506
are connected, respectively, to a plate line
510
. The MOSFET gates
504
x
and
506
x
are connected, respectively, to a word line
512
. The terminal of the MOSFET
504
the is not connected to the ferroelectric capacitor
500
is connected to a bit line
514
. Similarly, the terminal of the MOSFET
506
the is not connected to the ferroelectric capacitor
502
is connected to a complementary bit line
516
. A memory cell array
520
is configured containing the memory cell
508
, plate line
510
, word line
512
, bit line
514
, and complementary bit line
516
. Both the bit line
514
and the complementary bit line
516
are connected to a common sense amplifier
518
. In this device, moreover, a word driver
522
the makes the word line
512
either active (logic level “1” state) or inactive (logic level “0” state) is connected to each word line
512
. To the word drivers
522
are connected a row decoder
524
the provides signals for instructing each word driver
522
to operate. To each of the row decoders
524
are applied a row address selection signal (RAdd) and a row decoder energize signal (RAE). When both of these signals are applied to as row decoder
524
, the row decoder
524
connected to a specific word line, such as word line
512
, for example, is selected to provide a prescribed potential level. To each plate line
510
, moreover, is connected a plate driver
526
that puts the plate line
510
at a prescribed potential level. Each plate driver
526
is connected to a word line
512
and when the word line
512
becomes active, a signal that originates in the word line
512
is applied to the plate driver
526
. To the plate driver
526
is also applied a control signal (RS) for controlling the operation timing wherewith rows are selected. The plate driver
526
, moreover, produces an output corresponding to logic level “1” only when both the control signal (RS) and the signal originating in the word line
512
are applied thereto.
With reference to FIG.
11
and
FIG. 12
, the operation of reading data out from the ferroelectric memory device shown in
FIG. 11
will hereinafter be described.
FIG. 12
shows a timing chart for explaining data read operations in the conventional ferroelectric memory device described above. In
FIG. 12
, the symbol “L” represents a binary “0” (corresponding to logic level “0”), such as the level at ground potential, while the symbol “H” represents a binary “1” (corresponding to logic level “1”), such as the level at the power supply potential. In FIG.
12
(F), the potential changes (BL, /BL) of the bit line
514
and complementary bit line
516
are represented, respectively. Here, because the timing wherewith the low decoder energize (or activation) signal (RAE) is applied and the timing wherewith the row address selection signal (RAdd) is applied to the row decoder
524
are substantially coincident, the timing of the application of both of these signals is represented by a common continuous line in FIG.
12
(A). FIG.
12
(B) shows the timing wherewith the control signal (RS) is applied to the plate line
510
, FIG.
12
(C) the timing (WL) wherewith the word line
512
becomes either active or inactive, FIG.
12
(D) the timing (PL) wherewith the plate line
510
becomes either active or inactive, and FIG.
12
(E) the timing (SAE) wherewith the sense amplifier
518
is either energized or deenergized, respectively.
A read operation will be carried out as follows. First, at time t=t
0
, both the row decoder energize signal (RAE) and the row address selection signal (RAdd) are driven to the “H” level (FIG.
12
(A)), respectively. Then, the row decoder
524
is selected, and the output of the row decoder
524
is driven to the “H” level. When the row decoder
524
is selected, the word driver
522
is driven and the word line
512
(WL) is made active, that is, driven to the “H” level (time t=t
0
(FIG.
12
(C)). Thus a voltage is applied to the gates
504
x
and
506
x
of the two MOSFETs and the MOSFETs
504
and
506
are put in a conducting state. When the word line
512
(WL) becomes active, moreover, an “H” level signal is applied to the plate driver
526
connected to the word line
512
. (The plate driver becomes in a control signal waiting state).
Next, at time t=t
1
, when the control signal (RS) goes high “H” (FIG.
12
(B)), that is, when the control signal (RS) is applied to the plate driver
526
, “H” level signal is output from the plate driver
526
, and the plate line
510
(PL) becomes active (“H” level) (time t=t
1
(FIG.
12
(D))). Thereupon, the charge stored in the ferroelectric capacitor
500
begins to be distributed on the bit line
514
. Similarly, the charge stored in the ferroelectric capacitor
502
begins to be distributed on the complementary bit line
516
. Beginning at this time (t
1
), the potentials (BL and /BL) on the bit line
514
and the complementary bit line
516
change, respectively, in response to the distributed potentials (FIG.
12
(F)).
Next, a sense amplifier drive signal (SAE) is applied, at time t=t
2
, for example, to the sense amplifier
518
to which the bit line
514
and complementary bit line
516
are connected (to drive to an “H” level (FIG.
12
(E))). Thereby, the sense amplifier
518
latches the potential difference (&Dgr;V) between the potential (BL) appearing on the bit line
514
and the potential (/BL) appearing on the complementary bit line
516
to the potential difference with the power supply voltage level, transfers the difference to a data output circuit
528
, and thus outputs the requisite data (FIG.
11
).
After that, the ferroelectric capacitors
500
and
502
are restored by driving the control signal (RS) to the “L” level (time t=t
3
) (FIG.
12
(B)).
Last of all, the word line
512
(WL) is made inactive by driving the row address selection signal (RAdd) to the “L” level, (t=t
4
)(FIG.
12
(C)).
In general, the relative permittivity (dielectric constant) of a ferroelectric film is larger than the relative permittivity of a MOSFET oxidation film by roughly a two-digit factor. In the ferroelectric memory device described in the foregoing, moreover, the capacitances of the plurality of ferroelectric capacitors in the memory array are connected to the plate line
510
, and the gate capacitances of the plurality of MOSFETs are connected to the word line
512
. For that r
Burdett James R.
Hoang Huan
Oki Electric Industry Co. Ltd.
Venable
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