Static information storage and retrieval – Systems using particular element – Ferroelectric
Patent
1998-12-30
2000-09-12
Elms, Richard
Static information storage and retrieval
Systems using particular element
Ferroelectric
36518909, 365205, G11C 1122
Patent
active
061186880
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to memory devices embedded in electronic equipment and the like and, more particularly, to a ferroelectric memory device having a memory cell provided with a ferroelectric capacitor and to a method of driving the same.
BACKGROUND ART
In recent years, there has been proposed a ferroelectric memory device having a memory cell provided with a capacitor in which a capacitive film made of a ferroelectric material is disposed, resulting in a non-volatile memory device. As shown in FIG. 19, the ferroelectric material is such a material that, as an electric field applied thereto is increased gradually from 0, the amount of polarization caused therein also increases to reach a maximum value at point A but, as the electric field is reduced in reverse, the amount of polarization decreases slowly without retracing the previous transition process and does not reach 0 even when the electric field is reduced to 0, which causes a residual polarization indicated at point B. If a negative electric field is applied to the ferroelectric material and reduced gradually to 0, a residual polarization indicated at the point D is observed. One characteristic of the ferroelectric material is a so-called hysteresis curve or loop which causes a residual polarization responsive to the intensity and polarity of the electric field applied previously to the ferroelectric material.
By internally providing a memory cell with a ferroelectric capacitor composed of a ferroelectric film sandwiched between two conductor films and using, as stored data, the residual polarization of the ferroelectric film responsive to the polarity and magnitude of a signal voltage, the stored data can be preserved without being volatilized so that a so-called non-volatile memory device is implemented.
For example, U.S. Pat. No. 4,873,664 discloses the following two types of ferroelectric memory devices.
In the non-volatile memory device of the first type, each memory cell for storing 1 bit is composed of one transistor and one ferroelectric capacitor (1T1C). In this case, one dummy memory cell (reference cell) is provided for every 256 main memory cells (normal cells).
In the non-volatile memory device of the second type, each memory cell for storing 1 bit is composed of two transistors and two ferroelectric capacitors (2T2C) without using a dummy memory cell.
There is also a non-volatile memory device in which each memory cell for storing 1 bit is composed of two transistors and one ferroelectric capacitor (2T1C), as disclosed for example in U.S. Pat. No. 4,888,733.
Known examples of the ferroelectric material used in the ferroelectric capacitor include KNO.sub.3, PbLa.sub.2 O.sub.3 --ZrO.sub.2 --TiO.sub.2, and PbTiO.sub.3 --PbZrO.sub.3. There is also disclosed a ferroelectric material with extremely reduced fatigue compared with PbTiO.sub.3 --PbZrO.sub.3 in PCT International Publication WO 93/12542.
A description will be given to the operation of a conventional 2T2C ferroelectric memory device with reference to FIGS. 17 and 18.
FIG. 17 is an electric circuit diagram showing the structure of the conventional 2T2C ferroelectric memory device, in which a reference numeral 1 denotes a memory cell; 2 denotes a bit-line voltage control circuit; 3 denotes a sense amp circuit; BL, /BL denote bit lines; SN, /SN denote data accumulation nodes; WL denotes a word line; CP denotes a cell plate line; BP2 denotes a bit-line voltage control signal line; and SAE denotes a sense-amp control signal line.
In the memory cell circuit 1, memory cell transistors 11, 12 have respective drains connected to the bit lines BL, /BL, respective sources connected to the data accumulation nodes SN, /SN, and respective gates connected to the word line W1. Memory cell capacitors 13, 14 each having a ferroelectric film are interposed between the respective data accumulation nodes SN, /SN and the cell plate line CP.
In the bit-line voltage control circuit 2, respective NMOS transistors 21 and 22 for voltage control are interposed between the bit li
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Asari Koji
Hirano Hiroshige
Elms Richard
Matsushita Electronics Corporation
Nguyen Hien
Robinson Eric J.
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