Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-10-26
2001-02-20
Carroll, J. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C257S310000, C257S532000, C365S145000
Reexamination Certificate
active
06191441
ABSTRACT:
This application is based on Japanese Patent Applications No. 9-295878 and No. 9-295879 both filed on Oct. 28, 1997, and No. 10-297114 filed on Oct. 19, 1998, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1.) Field of the Invention
The present invention relates to a ferroelectric memory device, and more particularly a ferroelectric memory device suitable for a 1T-1C type memory which forms one memory cell by using one transistor and one ferroelectric capacitor, and to a method of driving a 1T-1C type memory.
2.) Description of the Related Art
A ferroelectric capacitor made of ferroelectric material interposed between a pair of electrodes produces polarization in an amount corresponding an applied voltage. The characteristics of a polarization amount relative to an applied voltage show hysteresis, and even if the applied voltage is turned off, there remains residual polarization. If residual polarization is formed corresponding in amount to input data, a non-volatile memory can be formed by using the ferroelectric capacitor. For example, an insulated-gate field effect transistor can be turned on or off in accordance with polarization of a ferroelectric capacitor whose one electrode is connected to the insulated gate of the transistor.
Products of a 2T-2C type ferroelectric random access memory (FeRAM) using two transistors and two capacitors per one memory cell are now available up to 64 k bits. However, a 1T-1C type FeRAM using one transistor and one capacitor per one memory cell is still under the development stage for practical application.
FIGS. 8A
to
8
C show a ferroelectric capacitor according to conventional techniques. As shown in
FIG. 8A
, on the surface of a p-type silicon substrate
51
, a floating gate electrode
53
of polysilicon or the like is formed, with a gate oxide film
52
being interposed between the substrate and the floating gate electrode. On this floating gate electrode
53
, a ferroelectric layer
54
is formed, and on this ferroelectric layer
54
, a control gate electrode
55
is formed. This lamination structure is patterned to form a gate electrode. A source region
61
and a drain region
62
are formed on both sides of the gate electrode by doping n-type impurities through ion implantation.
Consider that a positive voltage +V is applied to the control gate electrode
55
and thereafter this voltage is turned off. Upon application of a voltage of +V, the ferroelectric layer
54
induces polarization as shown in FIG.
8
A. This polarization remains and becomes residual polarization even after the applied voltage to the control gate electrode
55
is turned off. The residual polarization charges the floating gate electrode
53
positive and induces an n-channel
60
in the surface layer of the p-type silicon substrate
51
. The source region
61
and the drain region
62
are therefore electrically connected via the n-channel
60
.
As shown in
FIG. 8B
, consider that a negative voltage −V is applied to the control gate electrode
55
and thereafter this voltage is turned off. Upon application of a voltage of −V, the ferroelectric layer
54
induces polarization of a polarity opposite to that shown in FIG.
8
A. This polarization remains and becomes residual polarization even after the applied voltage to the control gate electrode
55
is turned off. The residual polarization charges the floating gate electrode
53
negative and extinguishes the channel in a surface layer of the p-type silicon substrate
51
. The source
61
and the drain
62
are therefore electrically cut off.
In the above manner, data can be stored in a non-volatile way by making the applied voltage to the control gate electrode
55
relative to the substrate
51
control the polarization of the ferroelectric layer
54
.
The ferroelectric memory shown in
FIG. 8C
has a series circuit of a capacitor C
2
and a capacitor C
1
, the former utilizing the gate oxide film
52
as the capacitor dielectric layer and the latter utilizing the ferroelectric layer
54
as the capacitor dielectric layer. Since the dielectric constant of the ferroelectric layer
54
is considerably higher than that of the gate oxide film
52
, the capacitance of the capacitor Cl tends to be larger than that of the capacitor C
2
.
As shown in
FIG. 8C
, as a voltage V is applied across the substrate
51
and the control gate electrode
55
, a voltage V
1
across the ferroelectric capacitor C
1
become less than a voltage V
2
across the series connected capacitor C
2
.
If the hysteresis characteristics of the ferroelectric capacitor require the voltage V
1
, a large voltage of V
1
+V
2
is required to be applied to the control gate electrode
55
.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a ferroelectric memory capable of writing data with a small voltage.
It is another object of the present invention to provide a ferroelectric memory having a novel structure.
It is a further object of the present invention to provide a 1T-1C type ferroelectric memory device having a simple structure.
It is a still further object of the present invention to provide a ferroelectric memory device capable of performing write operation by using only two lines, e.g. word and bit lines.
It is another object of the present invention to provide a novel drive method for a 1T-1C type ferroelectric memory device.
According to one aspect of the present invention, there is provided a ferroelectric memory device comprising: a semiconductor substrate; an insulated-gate field effect transistor including a gate insulating film formed on a surface of the semiconductor substrate, a gate electrode formed on the gate insulating film, and source and drain regions formed in a surface layer of the semiconductor substrate on both sides of the gate electrode; an insulating film formed over the surface of the semiconductor substrate and covering the gate electrode; a ferroelectric film formed on the insulating film; and a pair of capacitor electrodes formed on the ferroelectric film and facing each other, one of the pair of capacitor electrodes being electrically connected to the gate electrode.
Since a ferroelectric capacitor is formed by forming a pair of opposing electrodes on one surface of a ferroelectric layer, the ferroelectric capacitor having a desired capacitance can be formed. By disposing one of the opposing capacitor electrodes above the gate electrode, a stray capacitor of the capacitor electrode can be reduced.
According to another aspect of the present invention, there is provided a ferroelectric memory device comprising: an insulated-gate field effect transistor having a source, a drain, and an insulated gate; and a memory cell including a ferroelectric capacitor connected to the drain and the insulated gate.
By connecting a ferroelectric capacitor between the insulated-gate and the drain of an insulated-gate field effect transistor, a diode-connection field effect transistor can be formed. The rise potential (threshold value) of the diode-connection field effect transistor can be controlled by residual polarization of the ferroelectric capacitor.
Polarization in the ferroelectric capacitor can be controlled by a voltage applied across the drain and the source.
According to another aspect of the present invention, there is provided a method of driving a ferroelectric memory device which comprises: a plurality of bit lines disposed in parallel; a plurality of word lines disposed in parallel, the word lines crossing the bit lines; and a ferroelectric memory cell connected at each cross point between the bit and word lines, the ferroelectric memory cell including an insulated-gate field effect transistor having a source, a drain, and an insulated gate, and a ferroelectric capacitor connected across the drain and the insulated-gate, the method comprising the steps of: (a) connecting a selected word line to a ground potential and applying a first reference potential to other word lines and all the bit lines, to write data “1” in
Aoki Masaki
Eshita Takashi
Takauchi Hideki
Tamura Hirotaka
Armstrong, Westerman Hattori, McLeland & Naughton
Carroll J.
Fujitsu Limited
LandOfFree
Ferroelectric memory device and its drive method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Ferroelectric memory device and its drive method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Ferroelectric memory device and its drive method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2585990