Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2002-09-04
2004-09-14
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S149000, C365S200000
Reexamination Certificate
active
06791861
ABSTRACT:
This application claims the benefit of the Korean Application No. P2001-57274 filed on Sep. 17, 2001, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly, to a ferroelectric memory device capable of improving the sensing margin of a bitline by reducing capacitance between adjacent bitlines and a method for driving the ferroelectric memory.
2. Discussion of the Related Art
Generally, nonvolatile ferroelectric memory, i.e., ferroelectric random access memory (FRAM) has a data processing speed equal to that of dynamic random access memory (DRAM) and retains data even when power is turned off. For this reason, the nonvolatile ferroelectric memory has lately attracted considerable attention as a next generation memory device.
The FRAM and DRAM have similar structures as memory devices, but the FRAM includes a ferroelectric capacitor, which is characteristic of high residual polarization. Such a ferroelectric capacitor permits its data to be retained even when electric field is removed.
FIG. 1
is a conventional characteristic diagram showing a hysteresis loop of a general ferroelectric device. As shown in
FIG. 1
, the polarization induced by electric field maintains its state at a certain amount (i.e., at the state of “d” or “a”) without being erased due to the presence of residual polarization (or spontaneous polarization) even when electric field is removed. A nonvolatile ferroelectric memory cell can be used as a memory device such that the state of “d” or “a” correspond to the logic value of “1” or “0” respectively.
FIG. 2
is a schematic diagram showing a unit cell of the general nonvolatile ferroelectric memory device.
As shown in
FIG. 2
, the nonvolatile ferroelectric memory device includes a bitline B/L formed in one direction, a wordline W/L formed in a direction crossing the bitline B/L, a plate line P/L spaced apart from the wordline W/L in a parallel direction with the wordline W/L, a transistor T
1
having a gate electrode connected with the wordline W/L and a source electrode connected with the bitline B/L, and a ferroelectric capacitor FC
1
having a first terminal connected with a drain of the transistor T
1
and a second terminal connected with the plate line P/L.
A data input and output operation of the aforementioned nonvolatile ferroelectric memory device will be described below.
FIG. 3A
is a timing diagram showing a write mode operation of the nonvolatile ferroelectric memory device, and
FIG. 3B
is a timing diagram showing a read mode operation of nonvolatile ferroelectric memory device.
First, in the write mode operation, a chip enable signal CSBpad applied externally is enabled from high to low. At the same time, if a write enable signal WEBpad is applied from high to low, the write mode operation will start. Subsequently, if address decoding is activated in the write mode operation, a pulse applied to a corresponding wordline W/L will be transited from low to high in order to select a cell.
As described above, during a period of the wordline W/L maintaining at high state, a high signal with a certain period and a low signal with a certain period are sequentially applied to a corresponding plate line P/L. In order to write a logic value “1” or “0” in the selected cell, a high or low signal synchronized with the write enable signal WEBpad is applied to a corresponding bitline B/L.
In other words, a high signal is applied to the bitline B/L, and if a low signal is applied to the plate line P/L in the period during which the signal applied to the wordline W/L is high, a logic value “1” is written in the ferroelectric capacitor FC
1
.
And a low signal is applied to the bitline B/L, and if the signal applied to the plate line P/L is high, a logic value “0” is written in the ferroelectric capacitor FC
1
.
An explanation will be given below as to the read mode operation, data of which has been stored in a cell by the write mode operation.
As shown in
FIG. 3B
, if the chip enable signal CSBpad applied externally is enabled from high to low, all of bitlines B/L will be equipotential to a low voltage by an equalizer signal EQ before the corresponding wordline W/L is selected.
The corresponding bitline B/L becomes inactive. Then an address is decoded, and the corresponding wordline W/L is transited from low to high according to the decoded address in order to select the corresponding cell.
Subsequently, a high signal is applied to the plate line P/L of the selected cell in order to destroy the data corresponding to the logic value “1” stored in the ferroelectric memory. If the logic value “0” is stored in the ferroelectric memory, the corresponding data will not be destroyed.
As described above, the data destroyed or non-destroyed are output as values different with each other according to the principle of hysteresis loop, and thereby the logic value “1” or “0” is sensed by a sensing amplifier. In other words, as shown in the hysteresis loop of
FIG. 1
, if the data is destroyed, the “d” state is changed to the “f” state, whereas if the data is not destroyed, the “a” state is changed to the “f” state.
Thus, if the sensing amplifier is enabled after a constant time elapses, the logic value “1” is output in the case where the data is destroyed, while the logic value “0” is output in case where the data is not destroyed.
As described above, after the data is output by the sensing amplifier, it should be recovered to its original data, the plate line P/L disabled from high to low during the state in which a high signal is applied to the corresponding wordline W/L.
A conventional ferroelectric memory device and a method for driving the same will be described below with reference to the accompanying drawings.
FIG. 4
is a circuit diagram showing the conventional nonvolatile ferroelectric memory element.
As shown in
FIG. 4
, a unit cell of the conventional nonvolatile ferroelectric memory element formed in the row direction includes a first split wordline SW
1
and a second split word line SW
2
which are parallel with each other, a first bitline BL
1
and a second bitline BL
2
formed crossing the first and the second split wordlines SW
1
and SW
2
, a first transistor T
1
having a gate connected to the first split wordline SWL
1
and a drain connected to the first bitline BL
1
, a first ferroelectric capacitor FC
1
connected between a source of the first transistor T
1
and the second split wordline SWL
2
, a second transistor T
2
having a gate connected to the second split wordline SWL
2
and a drain connected to the second bitline BL
2
, and a second ferroelectric capacitor FC
2
connected between a source of the second transistor T
2
and the first split wordline SWL
1
.
FIG. 5
is another circuit diagram showing the conventional nonvolatile ferroelectric memory device.
As shown in
FIG. 5
, the conventional nonvolatile ferroelectric memory device includes a plurality of pairs of split word lines having a pair of a first and a second split wordlines SWL
1
, SWL
2
in the row direction, a plurality of pairs of bitlines having a pair of adjacent two bitlines BL
1
, BL
2
in a direction crossing the pairs of wordlines SW
1
, SW
2
, a plurality of sensing amplifiers SA located between the pair of bitlines BL
1
, BL
2
and serving to sense data received via both the bitlines BL
1
, BL
2
and transmit the data to a data line DL or a data bar line /DL.
Here, a sensing amplifier enabling part (not shown) outputs a sensing amplifier enable signal SEN to enable the sensing amplifiers, a selection switching part CS switches the bitlines, and additionally, the data lines are selectively formed.
FIG. 6
is a timing diagram showing an operation of the conventional nonvolatile ferroelectric memory element.
A period T
0
shown in
FIG. 6
prior to a period during which the first split wordline SWL
1
and the second split wordline SWL
2
are enabled to high, is precharged to a constant level for all the bitlines. Then, during a T
1
period, both the first
Kang Hee Bok
Kim Jung Hwan
Kye Hun Woo
Lee Geun Il
Park Je Hoon
Hynix Semiconductor INC
Jacobson & Holman PLLC
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