Ferroelectric memory device

Details Ferroelectric memory device Ferroelectric memory device

2006-06-15

2009-11-10

Dinh, Son (Department: 2824)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S065000, C365S185250, C365S203000

Reexamination Certificate

active

07616471

ABSTRACT:
A ferroelectric memory array includes a plurality of bit lines; a plurality of memory cells connected to the bit lines and storing predetermined data; and a plurality of sense amplifiers provided in correspondence with the bit lines and amplifying data that are read out from the memory cells. The sense amplifiers each include a first n-MOS transistor, a first voltage being supplied to a source of the first n-MOS transistor; a first precharge unit precharging a drain of the first n-MOS transistor to a second voltage, which is a positive voltage that is higher than the first voltage; a transistor control unit that lowers the drain voltage that has been precharged to the second voltage by controlling a resistance between the source and the drain of the first n-MOS transistor in accordance with a voltage on a corresponding bit line, when data stored in the memory cells is read out to that bit line; and a voltage control unit that lowers the voltage of the bit line in accordance with the lowering of the voltage of the drain.

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A Survey of Circuit Innovations in Ferroelectric Random-Access Memories, A. Sheikholeslami, et al., Proceedings of the IEEE, vol. 88 No. 5, May 2000, pp. 667-689.

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