Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2003-06-16
2004-11-23
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S063000, C365S206000, C365S207000, C365S210130, C365S202000
Reexamination Certificate
active
06822891
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a ferroelectric memory device which stores data in a nonvolatile fashion by use of a ferroelectric capacitor.
2. Description of the Related Art
A ferroelectric memory device stores binary data in a nonvolatile fashion according to the intensity of residual dielectric polarization of a ferroelectric capacitor. A memory cell of a conventional ferroelectric memory device is configured by connecting the ferroelectric capacitor and a transistor in series as in the case of a DRAM, for example. However, unlike the DRAM, since data is held depending on the intensity of residual dielectric polarization in the ferroelectric memory device, it is necessary to drive a plate line in order to read out signal charges onto a bit line. Therefore, in the conventional ferroelectric memory device, a plate line driving circuit is required to have a large area.
In order to cope with the above problem, a cell array system of the ferroelectric memory device which can reduce the area of the plate line driving circuit has been proposed by Takashima et al. (D. Takashima et al., “High-density chain ferroelectric random memory (CFRAM)” in Proc. VSLI Symp., June 1997, pp. 83-84). In the above cell array system, a memory cell is configured by respectively connecting two ends of the ferroelectric capacitor to the source and drain of a cell transistor, and a plurality of memory cells with the same configuration as described above are serially connected to configure a memory cell block. In the series connected TC unit type ferroelectric RAM, since the plate line driving circuit can be commonly used by eight memory cells, for example, the memory cell array can be integrated with a high integration density.
In the series connected TC unit type ferroelectric RAM with the above configuration, it is a common practice to arrange a dummy bit line outside the memory cell array and use the dummy bit line as a shield line by fixing the dummy bit line at ground potential, for example, so as to prevent occurrence of noise from the exterior of the memory cell array.
Further, a ferroelectric memory device in which a dummy bit line is arranged on the exterior of the memory cell array to compensate for capacitive coupling of the bit line on the end portion of the memory cell array has been proposed (Jpn. Pat. Appln. KOKAI Publication 10-200061).
It is known that the influence of noise (hereinafter referred to as coupling noise) caused by parasitic capacitance between wirings occurs when data which is read out onto the bit line arranged in the memory cell array is sensed. When two bit lines are arranged on both sides of a bit line with the same pitch and if the amount of coupling noise given to the bit line from one of the two bit lines is &dgr;, the amount of coupling noise 2&dgr; occurs by taking the coupling noise &dgr; given from the other bit line into consideration.
However, in the case of the bit line arranged on the end portion of the memory cell array, no coupling noise is given to the bit line from the dummy bit line fixed at the ground potential. Therefore, only the coupling noise &dgr; from one bit line is given to the bit line arranged on the end portion of the memory cell array. For example, when data is sensed in a two transistor-two capacitor (2T2C) system and it “1” is read out onto the bit line arranged on the end portion of the memory cell array and “0” is read out onto the adjacent bit line, the difference between the readout potentials is reduced by &dgr; and, as a result, the sense margin is reduced by &dgr;.
Thus, there occurs a problem that the sense margin is reduced due to an imbalance of coupling noise between the bit lines arranged on the end portion of the memory cell array, the retention characteristic is degraded and the yield rate is lowered.
BRIEF SUMMARY OF THE INVENTION
A ferroelectric memory device according to an aspect of the present invention includes a memory cell array having memory cells arranged in a matrix form. Each of the memory cells includes a cell transistor and a ferroelectric capacitor, one of source and drain regions of the cell transistor being electrically connected to a corresponding one of bit lines, a gate of the cell transistor being electrically connected to a corresponding one of word lines, the other one of the source and drain regions of the cell transistor being electrically connected to one electrode of the ferroelectric capacitor, the other electrode of the ferroelectric capacitor being electrically connected to a corresponding one of plate lines. It further includes a first dummy bit line arranged outside a bit line arranged on an end portion of the memory cell array and separated from the bit line arranged on the end portion of the memory cell array with an interval which is the same as a pitch between the bit lines in the memory cell array and having the same width as the bit line, and a first dummy memory cell electrically connected to the first dummy bit line and having the same structure as the memory cell.
A ferroelectric memory device according to another aspect of the present invention includes a first memory cell array having memory cells arranged in a matrix form. Each of memory cells includes a cell transistor and a ferroelectric capacitor, one of source and drain regions of the cell transistor being electrically connected to a corresponding one of bit lines, a gate of the cell transistor being electrically connected to a corresponding one of word lines, the other one of the source and drain regions of the cell transistor being electrically connected to one electrode of the ferroelectric capacitor, the other electrode of the ferroelectric capacitor being electrically connected to a corresponding one of plate lines. It includes a second memory cell array arranged adjacent to the first memory cell array to commonly use the bit lines electrically connected to the first memory cell array and having the same structure as the first memory cell array. Further, it includes a first dummy bit line arranged outside a bit line arranged on an end portion of the first memory cell array and separated from the bit line arranged on the end portion of the first memory cell array with an interval which is the same as the pitch between the bit lines in the first memory cell array and having the same width as the bit line, a first dummy memory cell electrically connected to the first dummy bit line and having the same structure as the memory cell. It includes a second dummy bit line arranged outside a bit line arranged on an end portion of the second memory cell array and separated from the bit line arranged on the end portion of the second memory cell array with an interval which is the same as the pitch between the bit lines in the second memory cell array and having the same width as the bit line, and a second dummy memory cell electrically connected to the second dummy bit line and having the same structure as the memory cell.
A ferroelectric memory device according to still another aspect of the present invention includes a memory cell array having memory cells arranged in a matrix form. Each of the memory cells includes a cell transistor and a ferroelectric capacitor, one of source and drain regions of the cell transistor being electrically connected to a corresponding one of bit lines, a gate of the cell transistor being electrically connected to a corresponding one of word lines, the other one of the source and drain regions of the cell transistor being electrically connected to one electrode of the ferroelectric capacitor, the other electrode of the ferroelectric capacitor being electrically connected to a corresponding one of plate lines. Further, it includes a dummy bit line arranged outside a bit line arranged on an end portion of the memory cell array, a capacitor having one electrode electrically connected to the dummy bit line, and a dummy bit line driving circuit having an output terminal electrically connected to the other electrode of the capacitor and input terminals electri
Hoya Katsuhiko
Rehm Nobert
Takashima Daisaburo
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