Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2003-03-20
2004-10-19
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S189090
Reexamination Certificate
active
06807083
ABSTRACT:
Japanese Patent Application No. 2002-81188 filed on Mar. 22, 2002, is hereby incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
The present invention relates to a ferroelectric memory device.
As one type of ferroelectric memory device, an active ferroelectric memory device having 1T/1C cells in which one transistor and one capacitor (ferroelectric) are disposed in each cell or 2T/2C cells in which reference cells are further disposed in each cell is known.
However, the memory area of the active ferroelectric memory device is increased in comparison with a flash memory or an EEPROM known as a nonvolatile memory device in which a memory cell is formed by one element, whereby an increase in capacity cannot be achieved.
Japanese Patent Application Laid-open No. 9-116107 discloses a ferroelectric memory device in which each memory cell is formed by one ferroelectric capacitor.
BRIEF SUMMARY OF THE INVENTION
A ferroelectric memory device in which each memory cell is formed by one ferroelectric capacitor has problems which must be solved for putting the ferroelectric memory device to practical use, such as a decrease in power consumption, an increase in drive speed, and problems occurring when turning the power on or off. The present invention may solve these problems.
A ferroelectric memory device according to the present invention comprises:
a plurality of word lines disposed in parallel;
a plurality of bit lines disposed in parallel so as to intersect the word lines;
a plurality of ferroelectric memory cells disposed at intersecting points of the word lines and the bit lines;
a word line driver section which drives the word lines;
a bit line driver section which drives the bit lines;
a first circuit which supplies a plurality of types of drive voltages to the word line driver section and the bit line driver section; and
a second circuit which is connected with end portions of the word lines and end portions of the bit lines, the second circuit short-circuiting all of the word lines and the bit lines.
According to the present invention, an equalize operation must be performed for a plurality of ferroelectric capacitors formed at each intersecting point of the word lines and the bit lines by setting electrodes of the word lines and the bit lines at the same potential after writing, reading, or rewriting data. If the equalize operation is performed using the second circuit, the equalize operation can be realized by utilizing charging and discharging of the word lines and the bit lines, whereby power consumption is decreased. This also enables the word lines and the bit lines to be precharged for the next operation mode by utilizing charging and discharging of the word lines and the bit lines.
A memory cell array in which the ferroelectric memory cells are arranged may be divided into a plurality of blocks, the word line driver section, the bit line driver section, and the second circuit being disposed in each of the blocks.
The short-circuit operation may be performed after writing data for which an increase in speed is comparatively unnecessary. If the word lines and the bit lines are short-circuited when turning the power on or when turning the power off, application of an unexpected voltage to the ferroelectric capacitor due to indetermination of transistors in the word line driver and the bit line driver or the first circuit can be prevented when turning the power on.
The second circuit may be directly connected with the end portions (one end portion or both end portions) of the word lines and the bit lines. This prevents occurrence of adverse effects caused by noise or an unexpected event due to indetermination of transistors during the short-circuit operation, since the transistors in the word line driver and the bit line driver or the first circuit are not interposed between the memory cell array and the second circuit. Therefore, a stable short-circuit operation can be secured. Moreover, since load capacitance to be connected is reduced due to a decrease in the length of a short-circuit path, the speed of the short-circuit operation is increased.
Before performing the short-circuit operation, potentials of the word line and the bit line selected during the operation mode may be predriven by the word line driver and the bit line driver so as to be close to a potential of the nonselected word lines or the nonselected bit lines. Since the number of selected word lines and selected bit lines is smaller than the number of nonselected word lines and nonselected bit lines, load capacitance connected with the selected word line and the selected bit line is small. Therefore, the charge and discharge speed of the selected word line and the selected bit line is comparatively high. If the word lines and the bit lines having different charge and discharge speeds are collectively short-circuited, an unexpected event may occur since the behavior of charge transfer cannot be estimated. Therefore, the selected word line and the selected bit line having a high charge and discharge speed are predriven before the short-circuit operation so that the potential of the selected word line and bit line are close to the potential of the nonselected word lines or the nonselected bit lines having a low charge and discharge speed.
When turning the power on, a plurality of short-circuit switches may be turned on for a predetermined period in the rise of a power supply potential immediately after turning the power on. When turning the power off, a plurality of short-circuit switches may be turned on for a predetermined period including a period after the power is turned off. This prevents application of an unexpected voltage to the ferroelectric capacitor by equalizing the word lines and the bit lines during a period in which the transistors in the word line driver and the bit line driver or the first circuit are indeterminate.
In order to realize the short-circuit operation when turning the power on and when turning the power off, a plurality of first short-circuit switches each connected between a common short-circuit line and one of among the word lines and the bit lines may be provided, and a plurality of second short-circuit switches may be provided in parallel to the respective first short-circuit switches. The first short-circuit switches may be turned on by a first control signal when turning the power on, and the second short-circuit switches may be turned on by a second control signal when turning the power off.
The short-circuit operation may equalize the word lines and the bit lines at a grounding potential by grounding the common short-circuit line. This enables a more stable equalize effect to be obtained by grounding the word lines and the bit lines by the short-circuit operation when turning the power on or when turning the power off due to the absence of residual charges.
The present invention may be suitably applied to a cross point or passive ferroelectric memory device in which each of the ferroelectric memory cells formed at intersecting points of the word lines and the bit lines is formed by only a ferroelectric capacitor.
REFERENCES:
patent: 5602784 (1997-02-01), Kojima et al.
patent: 2004/0071018 (2004-04-01), Nordal et al.
patent: 09-116107 (1997-05-01), None
Hogan & Hartson LLP
Le Vu A.
Seiko Epson Corporation
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