Ferroelectric memory device

Details Ferroelectric memory device Ferroelectric memory device

2001-12-27

2004-02-10

Tran, M. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S147000

Reexamination Certificate

active

06690599

ABSTRACT:

Japanese Patent Application No. 2001-393630, filed on Dec. 26, 2001, is hereby incorporated by reference in its entirety.
TECHNICAL FIELD
The present invention relates to a ferroelectric memory device. More particularly, the present invention relates to a simple matrix type ferroelectric memory device.
BACKGROUND
A simple matrix type ferroelectric memory device using only ferroelectric capacitors instead of cell transistors has a very simple structure and enables a higher degree of integration. Therefore, development of such a memory device has been expected.
Japanese Patent Application Laid-open No. 9-116107 discloses technology relating to a simple matrix type ferroelectric memory device and an operation method therefor.
A method of writing and reading data disclosed in Japanese Patent Application Laid-open No. 9-116107 is described below.
FIG. 9
is a view showing a memory cell array of a ferroelectric memory device.
The method of writing data is described below.
FIG. 10
is a timing chart in the case of writing data “1” into a ferroelectric capacitor Cm,N and writing data “0” into Cm, N+1. In the technology according to Japanese Patent Application Laid-open No. 9-116107, the data “1” is written into a memory cell by applying a voltage in a direction so that the potential of a selected sub-bit line is higher than the potential of a selected word line. The data “0” is written into the memory cell by applying a voltage in a direction so that the potential of the selected sub-bit line is lower than the potential of the selected word line.
Main bit lines MBLN and MBLN+1 are set to a ground voltage (0 V) at a time t1. At the same time, a selection gate line SL is set to 5 V from 0 V, a selected word line WLm is set to a power supply voltage VCC (3.3 V), and all non-selected word lines WL1 to WLm are set to the ground voltage (0 V). This causes the contents of the ferroelectric capacitors Cm,N and Cm,N+1 to be erased (data “0” is written).
At a time t2, the selection gate line SL and the selected word line WLm are set to the ground voltage (0 V), the main bit line MBLN is set to the power supply voltage VCC (3.3 V), and the main bit line MBLN+1 is set to (⅓) VCC (1.1 V).
At a time t3, the selection gate line SL is set to 5 V, the selected word line WLm is set to the ground voltage (0 V), and the non-selected word lines WL1 to WLM are set to (⅔) VCC (2.2 V). This causes the data “1” to be written into the ferroelectric capacitor Cm,N.
At a time t4, the main bit lines MBLN and MBLN+1 are set to (⅓) VCC (1.1 V), and the selection gate line SL and the word lines WL1 to WLM are set to the ground voltage (0 V), whereby the write operation is completed.
The method of reading data is described below.
FIG. 11
is a timing chart in the case of reading the data “1” stored in the memory cell Cm,N and reading the data “0” stored in the memory cell Cm,N+1, and rewriting the data “1” into the memory cell Cm,N and rewriting the data “0” into Cm,N+1.
At the time t1, a precharge signal &phgr;PC is set to the power supply voltage VCC (3.3 V), and a column select signal &phgr; is set to 5 V. This causes the main bit lines MBLN and MBLN+1 to be precharged to a precharge voltage VPC (0 V) before time t2. The main bit lines MBLN and MBLN+1 are respectively connected to nodes VN and VN+1 of sense amplifiers.
At the time t2, the precharge signal &phgr;PC is dropped to 0 V, thereby causing the main bit lines MBLN and MBLN+1 to be in a floating state. The selection gate line SL is set to 5 V from 0 V, and the selected word line WLm is set to the power supply voltage VCC (3.3 V) from 0 V. This causes the ferroelectric capacitors Cm,N and Cm,N+1 to be in a polarization state in which the data “0” is written.
At the time t3, the selection gate line SL and the selected word line WLm are set to 0 V. At the time t4, a sense enable signal &phgr;SE is set to the power supply voltage VCC (3.3 V). This causes sense amplifiers SAN and SAN+1 to be activated. As a result, the data “1” is latched by the sense amplifier SAN before a time t5, whereby the potential of the main bit line MBLN is set to the power supply voltage VCC (3.3 V). The data “0” is latched by the sense amplifier SAN+1, whereby the potential of the main bit line MBLN+1 is set to the ground voltage (0 V). The read operation is performed in this manner.
Since steps after the time t5 are rewriting steps, description thereof is omitted.
SUMMARY
The present invention may provide a ferroelectric memory device with improved operability.
A ferroelectric memory device according to the present invention comprises:
a memory cell array, in which memory cells are arranged, in a matrix, which comprises first signal electrodes, second signal electrodes arranged in a direction which intersects with the first signal electrodes, and a ferroelectric layer disposed at least in intersecting regions in which the first signal electrodes intersect with the second signal electrodes,
wherein, provided that the maximum absolute value of a voltage applied between one of the first signal electrodes and one of the second signal electrodes is Vs, a polarization value P of a ferroelectric capacitor comprising one of the first signal electrodes, one of the second signal electrodes, and the ferroelectric layer is within the range of:
0.1
P
(+
Vs
)<
P
(−⅓
Vs
)
when the applied voltage is changed from +Vs to −⅓Vs, and
0.1
P
(−
Vs
)>
P
(+⅓
Vs
)
when the applied voltage is changed from −Vs to +⅓Vs.
The polarization P(+Vs) is positive when the applied voltage is +Vs, and the polarization P(−Vs) is negative when the applied voltage is −Vs.
The difference between the polarization corresponding to the data “0” and the polarization corresponding to the data “1” can be increased if the polarization of the ferroelectric capacitor satisfies the above conditions. As a result, the ferroelectric memory device can be operated reliably. Specifically, operability of the ferroelectric memory device can be improved.
The ferroelectric memory device of the present invention may have at least any of the following features.
(a) The ferroelectric layer may comprise a compound containing at least Sr, Bi, Nb, and O as constituent elements.
In this case, the compound may have the formula:
SrBi
x
Nb
y
O
z
wherein x may be 1.5 to 2.5, y may be 1.5 to 2.5, and z may be 7 to 11.
In this case, the compound may have the formula:
SrBi
x
(Ta
w
Nb
1−w
)
y
O
z
wherein x may be 1.5 to 2.5, y may be 1.5 to 2.5, z may be 7 to 11, and w may be 0 to 0.9.
(b) The ferroelectric layer may comprise a compound without 90° domain.
In this case, the ferroelectric layer may comprise a compound having a tungsten bronze type crystal structure.
In this case, the ferroelectric layer formed using the compound may have the strongest peak of an XRD diffraction line determined using a wide-angle method at the (001) plane.
(c) The ferroelectric layer may comprise a compound containing at least Pb, Ti, and O as constituent elements.
In this case, the ferroelectric layer may comprise a single phase compound.
(d) The ferroelectric layer may comprise a compound containing at least Pb, Ti, Zr, and O as constituent elements.
In this case, the compound may have the formula:
Pb
x
(Zr
1−y
Ti
y
)O
z
wherein x may be 0.9 to 1.3, y may be 0.6 to 1.0, and z may be 2.8 to 3.4.
In this case, the crystal structure of the compound may belong to a tetragonal system.
The ferroelectric layer formed using the compound may have the strongest peak of an XRD diffraction line determined using a wide-angle method at the (001) plane.
(e) Information may be written into a selected memory cell by applying a write voltage between one of the first signal electrodes and one of the second signal electrodes in one of the memory cells, and
an absolute value of the write voltage may be less than an absolute value of a saturation voltage at which the remanent polariz

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